Ciena Senior Digital ASIC Designer

Elevate your career as a Senior Digital ASIC Designer at Ciena, focusing on innovative high-speed connectivity solutions. Lead and influence the design of next-gen telecommunications technology.

In this senior engineering role, you will guide the design and integration of ASIC technologies for Ciena's WaveLogic products. Collaborate closely with system engineers on architecture specifications while enhancing RTL designs, supporting tool flows, and validating prototypes in the lab setting.

Key Responsibilities: • Lead ASIC design and integration for WaveLogic products • Collaborate on architecture specifications with system engineers • Develop top-level RTL designs using various IP blocks • Manage tool flows facilitating the ASIC integration process • Validate designs through prototypes in a laboratory environment

Requirements: • Bachelor’s degree in a relevant engineering discipline • Over 5 years of experience in ASIC design • Proficient in Verilog, SystemVerilog, and Python • Strong analytical skills related to timing and synthesis • Excellent communication skills, both written and verbal

Contribute your expertise in ASIC design and help shape the future of networking with Ciena. #J-18808-Ljbffr