Lead ASIC Design Engineer for Optical Modems

Elevate your engineering career with Celero as a Senior ASIC Design Engineer focusing on next-generation optical modem design. Your digital design expertise will be crucial in developing cutting-edge technologies. Celero is searching for a Senior ASIC Design Engineer proficient in digital design and verification, particularly for optical transceiver projects. You must have at least four years of relevant experience and familiarity with Verilog or System Verilog. Engage in pivotal design responsibilities including synthesis, timing analysis, and performance optimization for optimal outcomes. Key Responsibilities:

• Design digital circuits employing HDL techniques
• Carry out timing analysis and formal verification processes
• Optimize designs for enhanced performance and power savings
• Conduct RTL verification to assert functionality
• Participate actively in design reviews to provide feedback

Requirements:

• Degree in Electrical or Computer Engineering
• 4+ years of experience in digital design and verification
• Expertise in HDLs, especially Verilog/System Verilog
• Understanding of ASIC design and verification practices
• Strong teamwork and communication skills

Apply your ASIC design knowledge at Celero to drive advancements in optical technologies. #J-18808-Ljbffr