Physical Design Engineering Manager

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at

Role Overview

Astera Labs is seeking a Physical Design Engineering Manager to lead a team of physical design engineers at our Toronto site, driving the implementation of connectivity ASICs within our Signal Connectivity Group. This group is responsible for products that enable high-speed serial connectivity including PCIe retimers, Ethernet retimers, and signal conditioning solutions deployed across the world’s largest AI clusters and hyperscale data centers.

As a Physical Design Manager Engineering Manager, you will combine hands‑on technical leadership with people management, owning physical design execution from RTL to GDSII while building and mentoring a high‑performing team. You will drive floorplanning, place‑and‑route, timing closure, and sign‑off for complex designs requiring deep understanding of high-speed physical layer interfaces and SerDes integration at TSMC advanced nodes. This role is fully on-site at our Toronto location.

Basic Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field; Master’s preferred.
• 12+ years of experience in physical design implementation of complex SoCs at advanced nodes (7nm and below).
• 2+ years of experience leading teams or projects with demonstrated ability to mentor and develop engineers.
• Hands‑on expertise across the physical design flow: synthesis, place‑and‑route, CTS, extraction, timing closure, EM-IR, DRC/LVS, and equivalence checking.
• Proficiency with Cadence Innovus and/or Synopsys Fusion Compiler/ICC2 and supporting toolchains.
• Strong scripting ability in Tcl, Python, and/or Perl.
• Professional attitude with the ability to prioritize a dynamic list of tasks, plan and prepare for customer meetings in advance, and work with minimal guidance.
• Entrepreneurial, open‑minded behavior and can‑do attitude. Think and act fast with the customer in mind.

Required Experience

• Build, lead, and mentor a physical design team, owning Physical Design execution and team development for Signal Connectivity Group products.
• Drive block and top‑level physical design implementation from floorplan through tapeout for retimer and signal conditioning ASICs.
• Own floorplanning, macro placement, power grid design, clock tree synthesis, and place‑and‑route for complex blocks and full‑chip designs.
• Drive timing closure at both block and full‑chip levels, developing and maintaining timing constraints and signoff methodology.
• Ensure DRC/LVS/EM-IR closure and physical verification sign‑off to foundry requirements.
• Integrate hard macros, high-speed SerDes, analog IP, and third‑party IP blocks, ensuring seamless physical integration at block boundaries.
• Collaborate with RTL, DFT, STA, EMIR, and verification teams to drive design convergence from synthesis through sign‑off.
• Work with IP vendors for both RTL and hard‑macro integration, ensuring placement constraints and routing guidelines are met.
• Drive team execution, hiring, career development, and sprint planning for the Toronto PD team.
• Establish physical design best practices, flow improvements, and quality checks to scale execution across multiple concurrent programs.
• Coordinate with global PD teams (San Jose, Irvine, Bangalore) to ensure consistent methodology and design quality.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.

Preferred Experience

• Deep understanding of high-speed SerDes physical layer, including equalization, CDR, and signal integrity considerations impacting physical design.
• Experience with PCIe, Ethernet, or retimer/signal conditioning ASIC implementation.
• Knowledge of physical layer timing challenges specific to high-speed serial interfaces.
• Hands‑on experience with UPF‑based multi‑voltage/multi‑power‑domain implementations.
• Familiarity with advanced packaging or multi‑die integration and its impact on physical design.
• Experience with ECO methodologies and DFT‑aware physical design.
• Knowledge of EMIR‑aware implementation techniques and early‑stage IR drop mitigation.
• Track record of building and scaling physical design teams through multiple tapeouts.
• Knowledge of agentic AI solutions for EDA automation.

Base salary range is CAD 180,000 to CAD 220,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives, and benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non‑binary people, veterans, parents, and individuals with disabilities.