RF/Analog Functional Verification Engineer

## \nCompany:\n\nQualcomm Canada ULC\n\n## Job Area:\n\nEngineering Group, Engineering Group \u003e ASICS Engineering\n\nGeneral Summary:\n\nQualcomm-Atheros is a leading provider of wireless and wired technologies for the mobile, networking, computing and consumer electronics markets. We\u0027re focused on inventing technologies that connect and empower people in ways that are elegant and accessible to all. Qualcomm Atheros\u0027 teams deliver cutting-edge products across every established wireless standard/protocol. \n \nWe are currently seeking candidates for positions involving the implementation of optimum system architectures, interfaces and logics for connectivity RF/Analog system. Successful candidates will be responsible for participating in development of leading-edge ASICs for multi-function mobile platforms. Candidates will work with engineers or develop unit-level and integrated-level test benches. Candidate will assist in synthesis and gate-level simulation tasks related to your module and will assist with timing of the entire chip. Candidate will leverage knowledge of wireless LAN, Bluetooth, and RF transceiver.\n\nNew Position \n \nIdeal candidate will have: \n \n*RTL Design\n\n*ASIC front-end experience \n*Scripting Languages knowledge (e.g. Perl or Python)\n\n## Responsibilities:\n\n * Develop and debug behavioral models for event-driven and mixed-signal simulation based on analog circuit design.\n\n * Create verification plans for radio and IP modules interfacing with SoC.\n\n * Build self-checking test benches and define test coverages and sequences.\n\n * Maintain scripts for netlist release and programming instruction generation.\n\n * Diagnose failed tests and manage bug tracking and resolution.\n\n * Contribute to methodology development, especially in AI/ML-enhanced verification flows.\n\n * Apply ML models to predict boundary values and optimize test coverage early in the design cycle.\n\n\n\n\n## \n\n## Skills/Experience:\n\n * Strong understanding of RF-analog and digital logic design.\n\n * Proficient in SystemVerilog, Python, Perl, C-Shell, and Cadence SKILL.\n\n * Experience with Cadence AMS/XCelium tools.\n\n * Familiarity with serial bus interfaces, register controllers, and state machines.\n\n * Knowledge of RF transceiver architectures, PLLs, ADCs, DACs.\n\n * Experience with UVM and functional verification of RF/mixed-signal chips.\n\n * AI/ML Fundamentals: Understanding of supervised/unsupervised learning, neural networks, and ML-based optimization.\n\n * Experience with ML libraries such as TensorFlow, PyTorch, Scikit-learn, and EDA-specific ML tools.\n\n * Ability to tailor ML models to analog/RF design topologies and verification tasks.\n\n * Experience with Prompt Engineering for AI/ML model interaction and optimization.\n\n\n\n\nMinimum Qualifications:\n\n\u2022 Bachelor\u0027s degree in Science, Engineering, or related field.\n\nApplicants: Qualcomm is an equal opportunity employer. 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Qualcomm is not responsible for any fees related to unsolicited resumes/applications.\n\nPay range and Other Compensation \u0026 Benefits:\n\n$90,100.00 - $135,100.00\n\nThe above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer.\n\nIf you would like more information about this role, please contact Qualcomm Careers.\n