RF/Analog Design Functional Modeling and Verification Engineer

Develop and debug behavioral models for event-driven and mixed-signal simulation based on analog circuit design. Create verification plans for radio and IP modules interfacing with SoC. Build self-checking test benches and define test coverages and sequences. Maintain scripts for netlist release and programming instruction generation. Diagnose failed tests and manage bug tracking and resolution. Contribute to methodology development, especially in AI/ML-enhanced verification flows. Apply ML models to predict boundary values and optimize test coverage early in the design cycle. Strong understanding of RF-analog and digital logic design. Proficient in SystemVerilog, Python, Perl, C-Shell, and Cadence SKILL. Experience with Cadence AMS/XCelium tools. Familiarity with serial bus interfaces, register controllers, and state machines. Knowledge of RF transceiver architectures, PLLs, ADCs, DACs. Experience with UVM and functional verification of RF/mixed-signal chips. AI/ML Fundamentals: Understanding of supervised/unsupervised learning, neural networks, and ML-based optimization. Experience with ML libraries such as TensorFlow, PyTorch, Scikit-learn, and EDA-specific ML tools. Ability to tailor ML models to analog/RF design topologies and verification tasks. Experience with Prompt Engineering for AI/ML model interaction and optimization. Coursework or thesis in Analog/RF/Mixed-Signal Design and Machine Learning is a strong plus. Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field.