Senior Asic Design Engineer Role Montreal

Elevate your career with Celero as a Senior ASIC Design Engineer, focusing on next‑gen optical modem technologies. Bring your digital design expertise to a transformative team.

We are seeking a Senior ASIC Design Engineer with a solid background in digital design and verification for optical transceiver projects. The candidate will possess a minimum of four years in the field, with a robust command of Verilog or System Verilog. Engage in critical design tasks, including synthesis, timing analysis, and optimization to ensure robust performance.

Key Responsibilities

• Develop digital circuit designs using HDL
• Execute timing analysis and formal verification tasks
• Optimize designs for performance and power efficiency
• Conduct RTL verification to validate functionality
• Attend design reviews to share insights

Requirements

• Degree in Electrical or Computer Engineering
• Over 4 years in digital design and verification
• Expert in HDLs, particularly Verilog/System Verilog
• Knowledge of ASIC design and verification methodologies
• Strong communication and teamwork skills

Apply your ASIC design talents at Celero and help shape future optical technologies.