Digital Design Verification Engineer H/F

Engineering Group, Engineering Group ASICS Engineering
Join the display design team as an ASIC Design Verification engineer where you will be part of a highly experienced multi-disciplinary and multi-site team that values collaboration, creativity, innovation and productivity. In this role you will help build next generation Display Processors that are key to delivering vivid and stunning visual experiences in the mobile, compute, automotive, and IoT markets. The candidate will work with industry leading edge HW Design Verification methodology and processes and provide expertise for next generation initiatives. Replacement Position.
Good working experience with C/C++
Strong knowledge of Object Oriented Programming (OOP) concepts
Hardware verification languages (HVL): Hardware description languages (HDL): Verilog and SystemVerilog
Bus/interconnect (AHB, AXI)
Strong knowledge of digital circuits and event-driven simulators
Knowledgeable with Perl, Python, TCL, tcsh, and GNU Make
Contribute to feature, core and sub-system verification during the design and development phase of next generation ASICs through C/RTL and Gate Level simulations.
Work closely with the design team to define verification requirements to ensure functional, performance and power correctness.
Participate in test plan development, execution and verification closure.
Contribute to creating/maintaining test benches, assertions, and functional coverage models.
Applies ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products.
software architecture, hardware architecture) to develop and execute an implementation strategy that meets system requirements and customer needs.
Evaluates all aspects of process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.
RTL to GDS Flow, Virtuoso) to execute and enable architecture and design of an individual block/SoC or IC Package.
Writes detailed technical documentation for EDA/IP/ASIC projects.
Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
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