Design Analysis Engineer

Engineering Group, Engineering Group ASICS Engineering
QCT’s DSP Team is actively seeking talented Physical Design Engineers to join our DSP PD team. As a Physical Design Engineer, you will innovate, develop, and implement DSP cores using state-of-the-art tools and technologies. This role requires strong expertise in physical design flow, tapeout readiness, and Power, Performance, and Area (PPA) optimization for advanced technology nodes.
Own and execute complete Physical Design flow from netlist to GDSII, including:
Floorplanning, power planning, IR-drop analysis
Placement, MMMC clock tree synthesis, routing
Perform PPA analysis and optimization to meet aggressive power, performance, and area targets.
Develop and enable low-power implementation methods and customized P&R strategies for area reduction and performance improvement.
Conduct RC extraction, signal integrity, crosstalk noise/delay analysis, and formal verification.
Collaborate with RTL, architecture, and verification teams to influence design decisions for optimal PPA.
Contribute to flow enhancements and automation using scripting (Perl/TCL, Python, Linux shell).
Bachelor’s or Master’s degree in Electrical Engineering or related field.

• 7+ years of industry experience in Physical Design for ASIC/SoC.
• Proficiency in scripting languages (Perl, TCL, Python) and Linux/Unix environments.

Knowledge of power integrity analysis (IR-drop, EM) and low-power design techniques.
Opportunity to lead tapeout and PPA optimization for high-performance, low-power designs.
Collaborative team environment with strong focus on innovation and technical excellence.
Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
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