Search Results: 22 vacancies
...primarily) and Microsemi devices (occasionally)
Develop and document RTL code to implement designs, coding in IP Integrator, HLS, SystemVerilog and VHDL.
Create detailed test benches and perform verification including detailed timing analysis
Create detailed test...
Suggested
Full time
Temporary work
...validation and verification plans;
Develop simulation verification test benches, verification components and bus-functional models in SystemVerilog, using standardized verification methodologies such as UVM;
Develop and implement on-target test environments;
Develop,...
Suggested
Full time
Worldwide
...searching globally for a number of key technical resources, including an ASIC Verification Specialist with strong expertise in UVM and SystemVerilog.
About the Position:
In this role you will use SystemVerilog and UVM, working from spec coverage-closed verified and...
Suggested
Full time
...yourself with complex tasks and are systematic in tackling problems. KEY RESPONSIBILITIES:
Contribute to the development of advanced Systemverilog-UVM based verification environments
Review and contribute to verification plans and design specifications
Employ a Coverage-...
Suggested
Full time
Internship
...Electrical Engineering, Computer Engineering, a related field, or equivalent experience
~5-10 years of design verification and SystemVerilog experience
~2+ years of experience in python
~ Expertise in developing with the UVM library
~ Experience with simulators such...
Suggested
Holiday work
Full time
Flexible hours
...d'essai de vérification pour la simulation, des composants de vérification et des modèles fonctionnels de bus en SystemVerilog, en utilisant des méthodologies de vérification normalisées telles que UVM;
Développer et mettre en œuvre des environnements...
Suggested
Full time
...a positive influence on team morale and culture.
Experience with task planning, program management, Agile
Must be expert in SystemVerilog, UVM.
Proficient in object-oriented programming, scripting (Ruby, Python, Perl), and low-level programming languages.
Deep system...
Suggested
Full time
Internship
Flexible hours
$57.4k - $106.6k per year
...s of RTL design experience
~ Good understanding of synchronous digital design concepts
~ Exposure to Verilog / SystemVerilog or VHDL language
Good analytical problem solving
Highly motivated to learn advanced coding techniques and best practices...
Suggested
Full time
Remote job
Flexible hours
3 days per week
...our team, you will get experience in:
Defining and tracking verification testplans
Designing and writing constrained-random SystemVerilog testbenches using UVM (Universal Verification Methodology)
Creating and examining Functional Coverage
Writing SystemVerilog assertions...
Suggested
Internship
Flexible hours
...of digital design concepts
~ Good understanding of C/C++ or any OOP based programming language
Exposure to Verilog / SystemVerilog or VHDL language
Exposure to HVL - based verification with expertise in SV & OVM /UVM would be an asset
Good...
Suggested
Full time
Remote job
Flexible hours
3 days per week
...and software engineers, to define verification requirements
Design and develop verification environments and test cases using SystemVerilog and UVM methodology
Execute and debug test cases, track and resolve issues
Ensure efficient use of resources and timely...
Suggested
Full time
...micro-architecture, RTL design and functional verification, synthesis, timing and formal verification.
• Proficiency of Verilog or SystemVerilog
• Experience with multi-clock domain designs.
• Experience in IP development.
• Knowledge in video/display standards a plus.
•...
Suggested
Contract work
Work experience placement
Internship
...10G/25G/56G/112G Ethernet, JESD204C, CPRI
Experience with lab tests for high-speed serial links
Experience with C/Verilog-A/systemVerilog
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio...
Suggested
Internship
...engineers responsible for delivering high-end mixed-signal designs.
Responsibilities include:
Setup UVM and VMM SystemVerilog testbenches to co-simulate mixed signal designs in both analog and digital coexist environment
analyzing/verifying the...
Suggested
...nature of this position, key qualifications include one or more of the following…
Modelling - experience in C/Matlab/Verilog-A/systemVerilog modeling of circuits and systems
Analog – solid background in high-speed analog CMOS circuit design
Digital – experience with...
Suggested
Internship
...complementary product, etc.
Experience & Qualifications :
At least 15 years of experience in hardware verification languages (SystemVerilog, SystemC, UVM).
At least 5 years of experience leading and managing a verification team.
Bachelor/Master in Electrical/...
...digital and mixed-signal ASIC circuits
Proficiency in RTL coding and verification using industry-standard tools (e.g., Verilog, SystemVerilog, UVM)
Strong programming skills including object-oriented programming
Working experience with digital logic design and...
Work experience placement
...equivalent technical degree in Electrical/Computer/Software Engineering
~8+ years of practical design verification experience using SystemVerilog UVM and ASIC verification.
~ Experience with functional coverage driven verification sign-off.
~ Experience contributing to...
Full time
Remote job
Worldwide
Flexible hours
...technical issues
Preferred Experience / Knowledge
Experience with digital logic design, simulation and debug using Verilog and SystemVerilog
Basic understanding of SerDes standards is an asset
Scripting experience (Bash, Tcl, Python, Perl) is an asset
Good...
...to completion
Preferred Experience / Knowledge
Experience with digital logic design, simulation and debug using Verilog and SystemVerilog
Basic understanding of SerDes standards is an asset
Scripting experience (Bash, Tcl, Python, Perl) is an asset
Good organization...
Internship
