...primarily) and Microsemi devices (occasionally)
Develop and document RTL code to implement designs, coding in IP Integrator, HLS, SystemVerilog and VHDL.
Create detailed test benches and perform verification including detailed timing analysis
Create detailed test...
Suggested
Full time
Temporary work
...searching globally for a number of key technical resources, including an ASIC Verification Specialist with strong expertise in UVM and SystemVerilog.
About the Position:
In this role you will use SystemVerilog and UVM, working from spec coverage-closed verified and...
Suggested
Full time
...problem-solving skills
~ Clear communication both written and oral
~ Highspeed design and timing closure
~ Designing RTL with SystemVerilog and Verilog
~ Capable of automating repetitive tasks using a variety of scripting languages
~1+ years of experience in RTL...
Suggested
...designers
Document, report and issue tracking
Preferred Skills & Experience
Knowledge of property checking language like SystemVerilog Assertion (SVA) and understanding of HDL languages such SystemVerilog or Verilog
Concept and flow of design verification, specific...
Suggested
Full time
...5+ years of related experience as well as experience in verifying designs at the chip level and block level.
Strong Verilog and SystemVerilog skills are required as well as in-depth knowledge of the UVM methodology.
Candidates will have knowledge of System Verilog...
Suggested
$57.4k - $106.6k per year
...s of RTL design experience
~ Good understanding of synchronous digital design concepts
~ Exposure to Verilog / SystemVerilog or VHDL language
Good analytical problem solving
Highly motivated to learn advanced coding techniques and best practices...
Suggested
Full time
Remote job
Flexible hours
3 days per week
...technical issues
Preferred Experience / Knowledge
Experience with digital logic design, simulation and debug using Verilog and SystemVerilog
Basic understanding of SerDes standards is an asset
Scripting experience (Bash, Tcl, Python, Perl) is an asset
Good...
Suggested
...Skills/credentials And Experience
~ B.S. or higher in Electrical Engineering, Computer Engineering, or a related field
~ Verilog, SystemVerilog, VHDL, or other suitable hardware description languages
~5+ years of experience developing / verifying high-performance FPGA...
Suggested
Full time
Remote job
Flexible hours
...micro-architecture, RTL design and functional verification, synthesis, timing and formal verification
Proficiency of Verilog or SystemVerilog
Experience with multi-clock domain designs
Experience in IP development
Design knowledge of data processing, encoder/...
Suggested
For contractors
Work experience placement
...signal engineers responsible for delivering high-end mixed-signal designs.
Main r esponsibilities include:
Setup UVM and VMM SystemVerilog testbenches to co-simulate mixed signal designs in both analog and digital coexist environment.
Analyzing/verifying the...
Suggested
...in Electrical Engineering, Computer Engineering, a related field, or equivalent experience
~8 years of design verification and SystemVerilog experience
~2+ years of experience in python
~ Expertise in developing with the UVM library.
~ Experience with...
Suggested
Holiday work
Full time
Flexible hours
...micro-architecture, RTL design and functional verification, synthesis, timing and formal verification.
• Proficiency of Verilog or SystemVerilog
• Experience with multi-clock domain designs.
• Experience in IP development.
• Knowledge in video/display standards a plus.
•...
Suggested
Contract work
Work experience placement
Internship
...of digital design concepts
~ Good understanding of C/C++ or any OOP based programming language
Exposure to Verilog / SystemVerilog or VHDL language
Exposure to HVL - based verification with expertise in SV & OVM /UVM would be an asset
Good...
Suggested
Full time
Remote job
Flexible hours
3 days per week
...our team, you will get experience in:
Defining and tracking verification testplans
Designing and writing constrained-random SystemVerilog testbenches using UVM (Universal Verification Methodology)
Creating and examining Functional Coverage
Writing SystemVerilog assertions...
Suggested
Internship
Flexible hours
...and software engineers, to define verification requirements
Design and develop verification environments and test cases using SystemVerilog and UVM methodology
Execute and debug test cases, track and resolve issues
Ensure efficient use of resources and timely...
Suggested
Full time
...nature of this position, key qualifications include one or more of the following…
Modelling - experience in C/Matlab/Verilog-A/systemVerilog modeling of circuits and systems
Analog – solid background in high-speed analog CMOS circuit design
Digital – experience with...
Internship
...equivalent technical degree in Electrical/Computer/Software Engineering
~8+ years of practical design verification experience using SystemVerilog UVM and ASIC verification.
~ Experience with functional coverage driven verification sign-off.
~ Experience contributing to...
Full time
Remote job
Worldwide
Flexible hours
...complementary product, etc.
Experience & Qualifications :
At least 15 years of experience in hardware verification languages (SystemVerilog, SystemC, UVM).
At least 5 years of experience leading and managing a verification team.
Bachelor/Master in Electrical/...
...digital and mixed-signal ASIC circuits
Proficiency in RTL coding and verification using industry-standard tools (e.g., Verilog, SystemVerilog, UVM)
Strong programming skills including object-oriented programming
Working experience with digital logic design and...
Work experience placement
...10G/25G/56G/112G Ethernet, JESD204C, CPRI
Experience with lab tests for high-speed serial links
Experience with C/Verilog-A/systemVerilog
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio...
Internship
...technical issues
Preferred Experience / Knowledge
Experience with digital logic design, simulation and debug using Verilog and SystemVerilog
Basic understanding of SerDes standards is an asset
Scripting experience (Bash, Tcl, Python, Perl) is an asset
Good...
...to completion
Preferred Experience / Knowledge
Experience with digital logic design, simulation and debug using Verilog and SystemVerilog
Basic understanding of SerDes standards is an asset
Scripting experience (Bash, Tcl, Python, Perl) is an asset
Good organization...
Internship
...Leadership skills with remote teams.
The ability to work independently, precisely and to drive innovation.
Proficient in SystemVerilog and UVM along with an understanding of C++.
Object oriented coding and verification solutions for productivity, performance, and...
Remote job
...Requirements
Experience in and enthusiasm for hands-on verification of digital hardware
Knowledge of and experience with SystemVerilog and UVM
Knowledge of and experience with Constrained-Random and Coverage-Directed verification
Scripting experience, including...