Senior Design Engineer- Emulation

Job Description

The Architecture Co-Verification team (ACOV) is an exciting, fast paced team responsible for enabling HW/FW development and co-verification of state-of-art System-On-Chip (SoC) devices using industry leading HW emulators (such as Cadence Palladium and Protium). The team is deployed in all aspects of SoC development phases from architectural exploration to post-silicon validation, HW/FW co-development, pre-silicon functional co-verification, pre/post-silicon performance testing, power analysis, and critical post-silicon investigations.

This Role Is Perfect For You If You

• Thrive in a fast-paced, technically challenging environment
• Love solving complex system-level problems that span both hardware and firmware
• Enjoy working with state-of-the-art emulation and FPGA platforms
• Want to build broad, deep expertise and high visibility across the organization

Responsibilities (But Are Not Limited To The Following)

• Port complex SoC RTL designs onto leading hardware emulators and FPGA platforms
• Design and develop emulation-specific hardware to enable robust pre-silicon subsystem and full-system co-verification
• Build a scalable, common test ecosystem that bridges pre-silicon and post-silicon environments
• Develop firmware and test content for system-level hardware/firmware co-verification
• Debug and resolve challenging issues in embedded multi-core, real-time systems running on emulators
• Leverage advanced protocol analyzers for deep-dive analysis, error injection, and performance optimization
• Track verification progress and product quality using industry-standard test and defect management tools
• Clearly communicate technical findings and solutions to engineering teams

Requirements/Qualifications

• BS/MS degree or higher in Electrical/Electronic Engineering, Computer Engineering, or a related field
• 5+ years of relevant work experience in hardware/firmware development or verification
• Hands-on experience with one or more serial storage protocols (SAS, SATA, or NVMe) and strong knowledge of PCIe
• Solid understanding of server and storage system architectures, including Windows and Linux host driver models
• Proficient Linux user with strong programming and scripting skills in C, Python, Tcl, and Bash
• Strong digital design and RTL coding experience using Verilog, SystemVerilog, or VHDL
• Experience creating and managing system validation test schedules and executing them effectivelyGood knowledge of processor architectures such as MIPS, ARM, or RISC-V, including JTAG, I2C, and firmware development
• Demonstrated ability to learn quickly in a fast-paced environment and a proactive, organized self-starter mindset

Desired Skills

• Excellent analytical, documentation, problem-solving, and communication skills
• Prior experience with hardware emulation (Cadence Palladium, Protium, or similar) is a strong asset
• Experience with RAID HBAs, SAS Controllers, and associated software testing strategies
• Familiarity with test automation frameworks, testing methodologies, and test tools
• Strong debugging skills in embedded multi-core real-time systems
• Knowledge of Embedded Linux and RTOS concepts (processes, threads, scheduling, synchronization, and memory management)
• Experience with Cadence emulation infrastructure and process flows is highly desirable
• Highly motivated team player who can drive personal and team goals

Travel Time

0% - 25%

Pay Range

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading IESPP program with a 6-month look back feature. Find more information about all our benefits at the link below:

Benefits of working at Microchip

The annual base salary range for this position is $86,000-$186,000.*

• Range is dependent on numerous factors including job location, skills and experience.