FPGA Compiler (Placer) Engineer

About Altera

At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

Position Overview

Altera is a leader in FPGA innovation, delivering programmable solutions that power AI, cloud computing, networking, and edge applications. Our compiler and tools teams are central to enabling customers to efficiently map complex designs onto advanced FPGA architectures. Altera is seeking a FPGA Compiler Engineer (Placer) to join our Compiler team in Toronto, Ontario Canada. This role focuses on developing and optimizing FPGA placement algorithms within the compiler toolchain, directly impacting performance, power efficiency, and overall design quality. The ideal candidate brings strong expertise in EDA algorithms, large-scale system optimization, and FPGA/ASIC physical design flows, along with a passion for solving complex, performance‑critical problems.

Key Responsibilities

• Placement Algorithm Development: Design, implement, and enhance FPGA placement algorithms to optimize timing, congestion, and resource utilization.
• Compiler Flow Enhancement: Contribute to the end‑to‑end FPGA compilation flow, working closely with routing, synthesis, and timing teams.
• Performance Optimization: Improve runtime performance, scalability, and quality of results (QoR) for large and complex customer designs.
• Timing-Driven Placement: Develop and refine timing‑aware placement strategies to support high‑frequency, performance‑critical designs.
• Cross-Functional Collaboration: Partner with architecture, routing, and STA teams to align placement strategies with FPGA device capabilities and constraints.
• Debug & Analysis: Analyze placement quality, congestion hotspots, and timing bottlenecks; drive improvements to convergence and design closure.
• Toolchain Integration: Integrate new placement capabilities into the compiler infrastructure and validate across diverse workloads.

Why Join Altera?

• Work on core compiler technology that directly impacts FPGA performance and usability
• Solve challenging algorithmic problems at scale
• Collaborate with world‑class teams across architecture, silicon, and software

Our compensation is designed to reflect the Canadian labour market. The actual salary offered may vary based on several factors, including the position’s location, as well as the candidate’s experience, skills, training, and job‑specific knowledge. In addition to base salary, we offer performance‑based incentive opportunities that reward both individual contributions and overall company success.

Estimated Salary Range: $129.1 – $187.0 CAD

Canadian work experience is not required for this role.

Applicants must be eligible for any required Canada export authorizations.

Job Type: Regular Shift: Shift 1 (Canada) Primary Location: Toronto, Ontario, Canada Additional Locations:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

About Altera

Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy‑to‑use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end‑to‑end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.

Qualifications

Minimum Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 6+ years of experience in FPGA/ASIC CAD, EDA tools, or related fields.
• Experience in algorithms and data structures (optimization, graph theory, heuristics)
• Experience with placement algorithms or physical design flows
• Experience in C/C++ and software engineering best practices
• Experience with placement techniques (analytical placement, simulated annealing, partitioning, clustering)
• Experience with Timing-driven and congestion-driven optimization
• Experience in ASIC or FPGA physical design methodologies
• Experience in solving complex, large-scale optimization problems with high performance and scalability requirements.

Preferred Qualifications

• Experience with FPGA toolchains (e.g., Quartus, Vivado)
• Knowledge of FPGA architectures and interconnect fabrics
• Familiarity with routing and timing closure techniques
• Experience with parallel or distributed algorithms for EDA tools
• Scripting experience (e.g., Python, Tcl) for tooling and automation