High Level Synthesis Compiler Engineer

Job Description

As a High Level Synthesis Compiler Engineer at Altera, you will focus on our compiler and the software that turns RTL and constraints into realizable designs: lowering, optimization, and integration with the broader implementation, timing, and debug flow.

You will build reliable and scalable tools; mentor talented engineers; and stay close to customers so their hardest design goals stay technically possible and practical in our tools.

Responsibilities

• Develop and optimize our compiler for the FPGA design flow: IR and lowering, analysis and transformation passes, correctness- and QoR-driven optimizations, and scalability (runtime and memory) on large designs.
• Work closely with customers to enable what they want to do: understand target applications, workflows, and success criteria; advocate for the capabilities, quality-of-results, and turnaround time they need; and turn that into concrete compiler and flow improvements—not only reactive support.
• Mentor talented engineers through code reviews, design reviews, and technical coaching; help grow ownership, design judgment, and execution quality across the team.
• Document and explain behavior, limitations, and workarounds for internal and external audiences where appropriate.
• Stay current with EDA and compiler technology (including LLVM/MLIR ecosystems where applicable), FPGA design practices, and relevant standards.

Compensation

Our compensation is designed to reflect the Canadian labour market. The actual salary offered may vary based on several factors, including the position's location, as well as the candidate's experience, skills, training, and job-specific knowledge. In addition to base salary, we offer performance-based incentive opportunities that reward both individual contributions and overall company success.

Estimated Salary Range : $124.1K - $179.7K CAD

We use artificial intelligence to screen, assess, or select applicants for the position. This posting is for an existing vacancy. Canadian work experience is not required for this role.

Qualifications

• Required: Bachelor's or Master's Degree in Electrical Engineering, Computer Engineering, Computer Science or a close related field.
• 8+ years of professional experience building compilers, LLVM/MLIR-based tools, or EDA/FPGA implementation software.
• Strong C++ for production systems (performance, multi-threading, large codebases).
• Hands-on experience with MLIR and/or LLVM (IR design, passes, backends, or integration with a larger compiler or EDA flow).
• Solid digital design and FPGA background: LUT/FF/BRAM/DSP primitives, clocks and timing, and how tool choices affect QoR.
• Familiarity with FPGA or ASIC implementation flows (synthesis, place-and-route, STA, constraints) and what can go wrong in real designs.
• Communication and collaboration: comfortable working with customers and translating their goals into actionable engineering work.
• Mentorship mindset: proven ability to develop other engineers through review, pairing, and clear technical guidance.

Preferred Qualifications

• PhD in Electrical Engineering, Computer Engineering, Computer Science or a close related field.
• Exposure to simulation, formal, or debug environments, or to high-level design flows (e.g., HLS) and how they map to the backend.
• Experience shipping software used by external customers or large internal user bases.

Job Type and Location

Job Type: Regular. Shift: Shift 1 (Canada). Primary Location: Toronto, Ontario, Canada. Additional Locations: [not specified].

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.