Fpga Digital Design Engineer
Kepler Communications Inc.
Our mission is to provide real-time on-orbit connectivity for critical missions, enabling a new era of data-driven intelligence and innovation. With 33 satellites launched to date, Kepler operates the first commercial optical data relay constellation, enabling real-time, continuous space communications while supporting advanced on-orbit compute and hosted payload capabilities.We’re on the hunt for a top-tier FPGA Digital Design Engineer to develop the next generation of our satellites.At Kepler, you’ll have the opportunity to work with a small dedicated team of engineers building the Kepler spacecraft. You will be responsible for the design and implementation of FPGA code either with a focus on DSP algorithms to modulate and demodulate signals on board our software defined radio (SDR), or embedded systems interfacing with processors and peripherals. To be effective you will need to participate in all phases of FPGA design flow (Simulation, Synthesis, Place & Route, Timing Closure and Hardware Testing). A good understanding of the intricacies of FPGA development would make a candidate standout.Option to work from home (100% remote) available.Key Responsibilities
Develop custom IP for new features of the Kepler satellite digital payloadsIterate on current DSP and interface designs to improve reliabilityWork with IP core vendors to integrate new functionality into the Kepler designsWork with lead engineers in developing the communications and network architecture of our future satellite constellationParticipate in conceptual design studies of new spacecraftRequired Skills & Qualifications
Bachelor’s Degree in Computer Engineering, Electrical Engineering or equivalent5+ yr. working experience with FPGA/RTL designVerilog, SystemVerilog, or VHDL with the willingness to learn or pivot to SystemVerilogXilinx FPGA(s). Specifically, Zynq and UltraScaleSolid understanding of timing principles, including clock domain crossing and timing closureStrong scripting skills (e.G Python, Tcl, csh/bash, etc.)Experience with FPGA tools (e.G Vivado, Quartus), HDL Simulation Tools (ModelSim)Bonus Points
Masters of Science in Computer/Electrical Engineering, or equivalentExperience in coherent digital demodulation of waveforms such as BPSK, QPSK, QAMExperience with memory mapped interfaces such as AXI, Wishbone, AvalonExperience with high-speed transceivers for protocols such as JESD204B, PCIe, SATAExperience with Linting tools, Questa Sim or Riviera-ProExperience with Xilinx Versal and RFSoCExperience designing printed circuit boardsKnowledge of radio-frequency electronics designKepler Communications is committed to fostering an inclusive, accessible environment, where all employees and customers feel valued, respected and supported. We welcome applications from: Women, Aboriginal persons, persons with disabilities, ethnic minorities, visible minorities, people who identify as LGBTQ+ and others who may contribute to diversification in our workplace.As part of our commitment to accessibility for all persons with disabilities, Kepler will, upon the request of the applicant, provide accommodation during the recruitment process to ensure equal access to applicants with disabilities. Please contact our People & Culture team, through our Career Page to make your accommodation needs known and we will consult with you to ensure suitable accommodation is provided.
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Develop custom IP for new features of the Kepler satellite digital payloadsIterate on current DSP and interface designs to improve reliabilityWork with IP core vendors to integrate new functionality into the Kepler designsWork with lead engineers in developing the communications and network architecture of our future satellite constellationParticipate in conceptual design studies of new spacecraftRequired Skills & Qualifications
Bachelor’s Degree in Computer Engineering, Electrical Engineering or equivalent5+ yr. working experience with FPGA/RTL designVerilog, SystemVerilog, or VHDL with the willingness to learn or pivot to SystemVerilogXilinx FPGA(s). Specifically, Zynq and UltraScaleSolid understanding of timing principles, including clock domain crossing and timing closureStrong scripting skills (e.G Python, Tcl, csh/bash, etc.)Experience with FPGA tools (e.G Vivado, Quartus), HDL Simulation Tools (ModelSim)Bonus Points
Masters of Science in Computer/Electrical Engineering, or equivalentExperience in coherent digital demodulation of waveforms such as BPSK, QPSK, QAMExperience with memory mapped interfaces such as AXI, Wishbone, AvalonExperience with high-speed transceivers for protocols such as JESD204B, PCIe, SATAExperience with Linting tools, Questa Sim or Riviera-ProExperience with Xilinx Versal and RFSoCExperience designing printed circuit boardsKnowledge of radio-frequency electronics designKepler Communications is committed to fostering an inclusive, accessible environment, where all employees and customers feel valued, respected and supported. We welcome applications from: Women, Aboriginal persons, persons with disabilities, ethnic minorities, visible minorities, people who identify as LGBTQ+ and others who may contribute to diversification in our workplace.As part of our commitment to accessibility for all persons with disabilities, Kepler will, upon the request of the applicant, provide accommodation during the recruitment process to ensure equal access to applicants with disabilities. Please contact our People & Culture team, through our Career Page to make your accommodation needs known and we will consult with you to ensure suitable accommodation is provided.
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