Low Power Asic Design Engineer

Drive low-power ASIC design, synthesis, and timing closure for complex SoC and IP designs supporting advanced semiconductor products.This ASIC Design Engineer develops power reduction strategies and optimizes power, performance, and area. The work includes static timing analysis, low-power verification, and workflow automation. Collaboration spans RTL design, physical design, and verification teams across time zones.Key Responsibilities:
Develop power reduction strategies across SoC and IP designsPerform synthesis and static timing analysis for PPA targetsOptimize dynamic and leakage power using EDA toolsRun UPF and CPF power intent verification checksSupport lint, CDC, timing, and power sign-off activitiesRequirements:
Strong ASIC synthesis and static timing analysis backgroundExperience with Synopsys Design Compiler and PrimeTimeKnowledge of clock gating, multi-Vt, and power gatingFamiliarity with UPF and CPF specificationsVerilog, SystemVerilog, and scripting proficiencyApply ASIC synthesis, power optimization, timing closure, and verification expertise to complex semiconductor SoC and IP designs.
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