Senior Digital Design Verification Engineer

Job Responsibility: 50148BR CANADA - Ontario - Mississauga

and Requirements

We are seeking a highly motivated individual with experience modeling complex digital systems. The successful candidate will design, integrate and maintain system models for use primarily in hardware design verification. These models will be used to verify the accuracy and functionality of our Verilog-based digital and analog designs. The candidate's work will produce models that are portable and reusable across several domains, both in verification and beyond. As a Senior Digital Design Verification Engineer, the individual in this role will implement models in C++ (or another appropriate language) that adhere to the specifications and requirements delivered by other teams. The candidate will also be responsible for support and maintenance of the delivered models. The candidate will be involved in verifying current and next generation Backplane Ethernet, PCIe, SATA and USB 2/3, and/or MIPI CPHY/DPHY SERDES products. The position offers an excellent opportunity to work with digital and mixed signal design engineers accountable for delivering high-end mixed-signal designs. You may be required to perform these types of tasks:

• Building models of SERDES components in C++ (or another appropriate language)
• Integrating models into other simulation environments, such as Matlab, Simulink, analog simulators, hardware emulation platforms, etc.
• Using models to predict system performance and the impact of architectural design choices
• Produce detailed documentation
• Defining and tracking test plans
• Designing and writing constrained-random SystemVerilog testbenches using UVM
• Defect and task tracking using software tools such as Jira
• Automating design and test flows with tools such as Jenkins
• SystemVerilog analog behavior modeling
• Unit-test development and code coverage analysis

Requirements:

• BSEE degree with 2 years directly experience.
• Experience writing scripts in languages such as Python and Unix shell
• C++ programming
• Capable with Verilog and SystemVerilog
• Knowledge of the UVM
• Excellent oral and written communication skills
• Well organized, methodical, detail oriented
• Experience debugging different types of code (C++, Python, Verilog, SystemVerilog, etc.)
• Matlab and Simulink experience are an asset

Our Silicon IP business is all about integrating more capabilities into an SoC — faster. We offer the world's broadest portfolio of silicon IP — predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities and meet unique performance, power, and size requirements of their target applications. At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Synopsys Canada ULC values the diversity of our workforce. We are pledged to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to applicants throughout the recruitment and employment process. Should you require an accommodation, please contact View email address on ca.edajobs.com.

Job Category

Engineering

Country

Canada

Job Subcategory

ASIC Digital Design

Hire Type

Employee