Ams Mixed-Signal Verification Engineer

Build mixed-signal verification environments at Synopsys using SystemVerilog, UVM, and AMS co-simulation for advanced SERDES IP. Work across analog and digital domains.As an AMS Design Verification Engineer, you will verify Ethernet and PCIe SERDES IP within Synopsys’ IPG Co-Simulation team. Define test plans, build UVM-based testbenches, and combine RTL, behavioral models, and transistor-level netlists. Debug complex interactions across analog and digital simulations while tracking coverage and completeness. The team supports engineers at different experience levels.Key Responsibilities:
Define verification plans for Ethernet and PCIe SERDES IPBuild UVM SystemVerilog testbenches with AMS co-simulation flowsVerify SERDES datapaths, equalization, CDR loops, and PLL behaviorDebug failures using HSPICE, XA, CustomSim, and VCSDevelop Python, Perl, and shell automation for regressionsRequirements:
Bachelor’s degree with five years’ relevant experience, or master’s degree with threeUnderstanding of analog and mixed-signal circuits and high-speed interfacesProficiency with SystemVerilog and UVM testbench developmentExperience with AMS simulation tools, coursework, or project exposureScripting skills in Python, Perl, or UNIX shellApply mixed-signal verification, SERDES, SystemVerilog, and automation expertise to Synopsys IP supporting production SoCs.
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