Layout Design, Staff Engineer- 18039

Category Engineering Hire Type Employee Job ID 18039 Base Salary Range $106000-$159000 Remote Eligible No Date Posted 07.07.2026

We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performan ce silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:
You are a passionate and detail-oriente d Layout Design Engineer with a strong foundation in analog and mixed-signal CMOS circuit layout. You thrive in a collaborative, fast-paced environment and are eager to contribute to the development of high-speed SerDes physical interfaces and supporting analog blocks. You possess a deep understanding of transistor-lev el design, deep submicron CMOS technologies, and the nuances of layout effects and reliability. Your expertise extends to floor planning, layout entry, and quality validation, and you are adept at designing for portability across multiple foundry nodes. You are familiar with signal integrity challenges, ESD and latch-up mitigation, and have a keen eye for optimizing layouts for performance and reliability. If you are looking to make a tangible impact in a global, innovative company and are excited to work alongside talented professionals from around the world, Synopsys is the place for you.

What You'll Be Doing:
* Designing and implementing complex analog and mixed-signal CMOS circuit layouts, with a focus on high-speed SerDes physical interfaces.
* Collaborating with circuit designers to translate schematics into robust, manufacturable layouts that meet performance, power, and area requirements.
* Performing floor planning, layout entry, and comprehensive verification to ensure design quality and compliance with foundry rules.
* Applying advanced techniques to mitigate signal integrity issues, ESD, and latch-up risks, including differential routing, shielding, and substrate biasing.
* Optimizing layouts for reliability, matching, and minimizing parasitic effects such as EM and IR drop.
* Supporting design porting activities to enable seamless migration of layouts across multiple foundry nodes and technology platforms.
* Documenting layout methodologies, best practices, and validation results to support knowledge sharing and continuous improvement.

What You'll Need:
* Bachelor or advanced degree in Electrical or Computer Engineering (or equivalent) with a solid background in transistor-lev el design.
* 5+ years of experience in analog and mixed-signal CMOS layout design, including complex integrated circuits.
* Expertise in deep submicron CMOS technologies and layout effects (matching, reliability, proximity, EM, IR, etc.).
* Proficiency in layout floor planning, verification, and quality validation using industry-stand ard EDA tools.
* Strong knowledge of signal integrity, ESD, and latch-up mitigation techniques.
* Familiarity with UNIX operating systems and scripting languages (TCL, Python) is a plus.
* Experience with Synopsys EDA tools is highly desirable.

Who You Are:
* Detail-oriente d and quality-focuse d, with a commitment to delivering robust and reliable designs.
* Excellent communicator, able to articulate technical concepts clearly to diverse audiences.
* Collaborative team player who builds productive relationships and networks effectively.
* S elf-motivated, organized, and able to manage multiple priorities in a dynamic environment.
* Strong problem-solvin g skills and critical judgment, with a proactive approach to overcoming challenges.
* Adaptable and eager to learn new technologies and methodologies.

The Impact You Will Have:
* Accelerate the development of cutting-edge silicon IP, enabling faster integration of advanced capabilities into SoCs.
* Enhance the performance, reliability, and manufacturabil ity of high-speed interface solutions for next-generatio n applications.
* Reduce time-to-market and risk for customers by delivering high-quality, validated layout designs.
* Contribute to the innovation of analog and mixed-signal design methodologies within a global team.
* Support the creation of differentiated products that power the Era of Smart Everything, from AI to IoT and beyond.
* Foster a culture of collaboration, knowledge sharing, and technical excellence within the team and across the organization.

The Team You'll Be A Part Of:
You will join a dynamic, international team focused on developing high-speed SerDes physical interfaces and supporting analog blocks for advanced SoC solutions. Our team values innovation, collaboration, and technical excellence, working closely with circuit designers, verification engineers, and global partners to deliver industry-leadi ng silicon IP. We foster a supportive environment where knowledge sharing and continuous learning are encouraged, and where your contributions will directly impact the success of our products and customers.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the Comp & benefits during the hiring process.
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Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact View email address on careers.synopsys.com .