Senior Memory Interface Verification Engineer Ahuntsic Cartierville (Ahuntsic-Cartierville)

Transform memory interface capabilities as a Senior Memory Interface Verification Engineer at Synopsys. Combine your expertise in UVM and SystemVerilog to enhance product quality and reliability.

This senior role focuses on the design and execution of robust verification processes for innovative memory interface IP. You’ll work alongside architecture teams to develop explicit verification plans and utilize advanced debugging skills to resolve challenges efficiently. Your role includes mentoring teammates, empowering them through shared knowledge and collaboration, promoting an inclusive team culture.

Key Responsibilities

• Drive development of verification strategies for memory IP
• Create effective UVM testbenches and case scenarios
• Collaborate in technical reviews across project phases
• Tackle verification challenges with analytical and debugging skills
• Foster the growth of junior engineers through mentorship

Requirements

• Solid experience with SystemVerilog and verification techniques
• Proficient in Python or similar scripting languages
• Acquainted with Linux development environments
• Deep understanding of UVM and memory protocols
• Degree in Electrical or Computer Engineering

Bring your analytical skills and passion for technology to help shape the future of semiconductor solutions at Synopsys.

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