Principal Ams Layout Engineer - 16701 (Markham)

We Are

At Synopsys, we drive the innovations that shape how the world lives and connects. Our technology powers the Era of Pervasive Intelligence—from autonomous vehicles to machine learning systems. As a global leader in chip design, verification, and IP integration, we enable the creation of high‑performance silicon and world‑class software. Join us and help transform the future through continuous technological advancement.

You Are

You are an experienced engineering leader with deep expertise in high‑speed analog and mixed‑signal layout. Your background in multi‑Gbps NRZ and PAM‑based SerDes, spanning advanced CMOS, FinFET, and GAA nodes, sets you apart. You excel in environments that value innovation, precision, and collaboration, and you are driven by the challenge of building repeatable, scalable methodologies that empower global engineering teams.

You translate complex technical challenges into actionable workflows, communicate clearly across interdisciplinary teams, and align stakeholders around shared goals. Mentoring and knowledge sharing come naturally to you. You thrive in fast‑moving environments, balancing multiple priorities while inspiring excellence in those around you. If you are ready to make a meaningful impact at a global leader in semiconductor technology, Synopsys is your next destination.

What You’ll Be Doing

• Define and manage layout scope, effort, schedules, deliverables, and customer‑specific requirements.
• Accelerate layout development for high‑speed SerDes IP to meet quality, schedule, and budget objectives.
• Act as the primary technical interface for customers and internal teams; present project status, risks, and mitigation plans.
• Gather customer requirements and translate them into clear technical specifications and workflow improvements.
• Perform hands‑on debugging and root‑cause analysis of complex layout issues; apply expertise to problem isolation and resolution.
• Collaborate on layout approaches considering advanced packaging (2.5D/3D, interposers, bump strategy, etc.) where applicable.
• Develop, validate, and refine end‑to‑end layout workflows that improve quality, consistency, and efficiency.
• Innovate analog/mixed‑signal layout methodologies using industry‑standard tools and internal automation.
• Ensure signoff quality across DRC/LVS, EM/IR, reliability, parasitics, and tapeout readiness.
• Create and maintain technical documentation, workflow guides, specifications, and customer‑facing deliverables.
• Ensure documentation is scalable, maintainable, and supports long‑term product evolution.
• Mentor junior engineers, promote best practices, and foster cross‑team knowledge sharing.

The Impact You Will Have

• Strengthen the quality and competitiveness of next‑generation high‑speed SerDes IP for advanced technologies.
• Drive methodology innovation that enhances efficiency and first‑time‑right success across multiple global product lines.
• Shape customer engagement by transforming complex requirements into actionable engineering strategies.
• Influence long‑term roadmaps for layout methodology, automation, and advanced‑node design practices.
• Elevate team capabilities through mentorship, coaching, and a culture of continuous improvement.
• Enable predictable, high‑quality program execution, directly accelerating customer product success and time‑to‑market.

What You’ll Need

• In‑depth familiarity with high‑speed SerDes layout and analog/mixed‑signal circuits.
• Experience with multi‑Gbps NRZ and PAM4 SerDes is a strong advantage.
• Expertise in:
  • High‑speed/signal‑integrity layout (differential routing, shielding, clock/data optimization, inductor/tcoil)
  • ESD design constraints and latch‑up mitigation
  • Custom digital layout (logic cell layout, logic‑path routing)
  • Reliability‑driven layout (EM, IR, self‑heat)
  • Parasitic‑aware layout (matching, symmetry, proximity effects)
  • Porting‑friendly layout practices across nodes and foundries
• Strong hands‑on debugging ability—problem isolation and root‑cause layout debugging are strongly desired.
• Proficiency in Synopsys Custom Compiler (or equivalent custom layout tools).
• Experience with verification tools such as ICV, Star‑RCXT, and PERC (or equivalents).
• Experience using Jira/Atlassian or similar project tracking platforms.
• Knowledge of advanced packaging (2.5D/3D, interposers, bump strategy, etc.) is a plus.

Who You Are

• Innovative and proactive in solving complex engineering challenges.
• Highly collaborative and effective across interdisciplinary teams.
• A strategic thinker who balances deep technical insight with broader product vision.
• An effective communicator able to articulate complex concepts to diverse audiences.
• A dedicated mentor who supports the growth and development of others.
• Adaptable, resilient, and capable of managing multiple fast‑paced initiatives.

The Team You’ll Be Part Of

You will join the High‑Speed Mixed‑Signal IP Layout Team—an advanced physical design group building full‑custom analog and ASIC layout solutions for high‑performance integrated circuits. The team is known for its collaborative culture, modern tool ecosystem, and commitment to innovation. As a Principal Engineer, you will work closely with experienced layout engineers, circuit designers, and CAD specialists to define best‑in‑class methodologies and deliver high‑quality solutions to Synopsys customers worldwide.

Rewards and Advantages

Synopsys offers a comprehensive suite of health, wellness, and financial benefits to support you and your family. Your recruiter will share details about compensation and benefits during the hiring process.

Equal Opportunity

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact View email address on ca.talent.com.