Average salary: $32,128 /yearly
More statsSearch Results: 5 vacancies
...level tests in Verilog or System Verilog
Defining Clock/Reset domain crossing design constraints and evaluating violations using CDC/RDC tools.
Defining synthesis design constraints and resolving STA issues as well as gate-level simulation failures.
Enhancing and...
Suggested
...well as gate-level simulation failures
Defining Clock/Reset domain crossing design constraints and evaluating violations using CDC/RDC tools
Enhancing and maintaining existing SERDES PHY IP
Interacting with Application Engineers for customer support and resolving...
Suggested
...verification experience in the industry
Must have hands-on experience with multiple clock domain design
Have experience with CDC/RDC/LINT tools
Have experience in defining synthesis constraints and STA
Good understanding of digital signal processing
Good organization...
Suggested
...in RTL design(Verilog or System Verilog)
Must have hands-on experience with multiple clock domain design
Have experience with CDC/RDC/LINT tools
Have experience in defining synthesis constraints and STA
Good understanding of digital signal processing
Good organization...
Suggested
...verification experience in the industry
Must have hands-on experience with multiple clock domain design
Have experience with CDC/RDC/LINT tools
Have experience in defining synthesis constraints and STA
Good understanding of digital signal processing
Good organization...
Suggested
