Verification Engineer

Verification Engineer Job Description Template

Our company is looking for a Verification Engineer to join our team.

Responsibilities:

  • ASIC verification including writing verification plans, verification environment development, behavioral model development and test case writing;
  • Develop and execute SoC test plans and work with the design team to ensure required test coverage;
  • Assist the FPGA emulation team as required;
  • Supporting regression runs (project dependent);
  • Work with other teams within the organization including system modelling and L1 control and L2/3 protocol stacks;
  • Working with simulation environments based on UVM.

Requirements:

  • 2 years experience working with the verification of complex systems at all levels, from block to full SoC;
  • Proficient in hardware description languages (preferably Verilog), and verification languages such as System Verilog;
  • Excellent communication skills, both written and verbal;
  • Experience in cellular and/or wireless communications systems would be a considerable benefit;
  • Execution of test plans in directed or randomized environments.