Senior verification engineer Job Description
Senior verification engineer Job Description Template
A Senior Verification Engineer spearheads the process of testing and validating system designs to ensure optimal performance. Responsibilities encompass developing verification plans, executing tests, and troubleshooting system errors.
Responsibilities:
- Develop and execute verification plans for complex designs
- Define and implement verification methodologies and test plans
- Design and develop test benches and test cases using SystemVerilog and UVM
- Debug and root cause failures to ensure functional correctness
- Collaborate with design and software teams to ensure timely delivery of products
- Mentor and guide junior verification engineers
- Stay up to date with industry trends and incorporate best practices
Requirements:
- Minimum of 5 years of experience in the semiconductor industry
- Expertise in verification methodologies and tools such as UVM, SystemVerilog, and Verilog
- Strong understanding of ASIC design flow and experience in verifying complex ASICs
- Experience in developing and executing verification plans, testbenches, and testcases
- Ability to debug complex design and testbench issues and provide solutions
- Excellent communication and collaboration skills to work effectively with cross-functional teams
- Bachelor's or Master's degree in Electrical Engineering or Computer Science is preferred
- Experience in leading small teams of verification engineers is a plus
