Senior Asic Ip Integration Engineer

Lead complex AMD ASIC IP integration with PCIe, power-aware flows, automation, and cross-functional technical direction.As an ASIC Design Engineer, PCIe IP Enablement, you will own complex digital IP or subsystem work from architecture through tape-out. Your responsibilities span PCIe integration, RTL implementation, low-power design, flow development, and front-to-back execution. You will also support technical decisions and mentor engineers.Key Responsibilities:
Lead AMD PCIe IP integration and SoC implementationDrive flow development, automation, and scriptingAnalyze complex problems and summarize solution optionsCoordinate technical and schedule discussions across sitesCollaborate with IP, Physical Design, and SoC teamsRequirements:
End-to-end ownership of complex ASIC IP or subsystemsExperience with integration, implementation, and version controlKnowledge of UPF or CPF power-aware design flowsFamiliarity with tile flow, repeaters, SRAM, ECO, and DFxBachelor's or Master's degree in Electrical or Computer Engineering preferredCombine ASIC ownership, PCIe integration, automation, and low-power expertise while directing high-quality AMD design execution.
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