Memory Interface Verification Engineer at Synopsys
Synopsys
Elevate your engineering career as a Senior Memory Interface Verification Engineer with Synopsys. Leverage your expertise in UVM and SystemVerilog to enhance verification processes and product quality. This senior role emphasizes developing robust verification strategies for state-of-the-art memory interface IP. Collaborate with architecture teams to create transparent verification plans, and apply advanced debugging skills to solve complex challenges. You’ll also play an integral part in mentoring junior engineers, enhancing team collaboration, and fostering an inclusive culture. Key Responsibilities:
- Drive verification strategy development for memory interface IP
- Create efficient UVM testbenches and test scenarios
- Collaborate on technical reviews during all project phases
- Use analytical skills to tackle verification challenges
- Mentor junior engineers to support their growth
- Strong experience in SystemVerilog and verification techniques
- Proficiency in Python or similar scripting languages
- Familiarity with Linux development environments
- Comprehensive understanding of UVM and memory protocols
- Degree in Electrical or Computer Engineering
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