Principal Analog Layout Engineer

Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact. The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions and are one of the main contributors to Ciena's success in the telecommunications industry. Successful candidates will be joining a vibrant team with a proven track-record of success over 30-years of evolution and revolution in the advancement of high-speed circuits used in broadband fiber-optic modems. This team pioneered the introduction of the world’s first high-speed DAC and ADC analog macros that ushered in the era of coherent fiber-optic product solutions. Your role as an analog layout engineer will be to drive and implement best-in-class high-speed analog layouts that extract the highest performance from the world’s most advanced CMOS and BiCMOS technologies. These analog macros include electrical interface-facing DAC and ADC based SERDES solutions for 112G and 224G, optical-line-facing high-speed DAC and ADC circuits interfacing with optical modulators and detectors, transimpedance amplifiers, modulator driver circuits, and critical precision analog circuits for control and monitoring functions, etc. Develop block and macro level layouts including floor-planning, placement, routing and optimization. Carry out layout feasibility studies on various circuit designs in collaboration with senior analog designers. Conduct thorough verification checks such as DRC, ANT, LVS, PERC, EM, IR to ensure the final layout possesses the highest level of quality. Mentor junior layout team members as applicable who may assist with some aspects of the overall layout implementation. What technical experience and personal skills are required for this role? Bachelor's or higher degree in Electrical Engineering or related field, with 5+ years of relevant industry experience. Proficient in layout techniques for Floor Planning, device matching, minimizing parasitics, RF shielding, EM, IR drop, ESD and high-frequency routing. Meticulous attention to details, ensuring the highest level of accuracy and quality in all layout designs. Familiarity with semiconductor manufacturing processes and foundry technologies. Ability to thrive in a fast-paced, dynamic work environment and adapt quickly to changing project requirements. Solid understanding of RC delay, electromigration, and coupling effects. The annual salary range $138,000 - $220,400 CAD. Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence. Ciena values the diversity of its workforce and respects its employees as individuals. Ciena is an Equal Opportunity Employer, including disability and protected veteran status.