Senior Program Manager
Stathera, Inc.
Stathera is transforming the timing industry with MEMS-based timing technology. Our products combine differentiated MEMS resonators with mixed-signal ASIC design to deliver precise, stable and power-efficient timing for connected devices, communications and data infrastructure. We are a growing, fabless team taking breakthrough technology from development to customer-ready, high-volume products.
INTRODUCTION TO THE ROLEYou will be the single accountable owner for delivering Stathera's semiconductor products, from concept through production release and customer ramp. You own the integrated plan, the schedule, the program budget and the readiness gates, and you are accountable for hitting customer sampling, qualification and design-win commitments.
You will lead a cross-functional team spanning MEMS, ASIC, packaging, test, product engineering, operations and external manufacturing partners. You do not manage these engineers directly;
you drive outcomes through clear plans, sharp decisions and disciplined follow-through. Success means the program ships on time, to spec, at target cost.
Reports to: Chief Operating Officer
Travel: up to 20%, including Asia
What you will ownEnd-to-end program delivery
Own each program from concept and requirements through design, tape-out, first silicon, engineering and customer samples, qualification and production release.
Build and own the integrated Plan of Record: scope, milestones, critical path, dependencies, resources and budget across MEMS, ASIC, package and test.
Run a phase-gate process with defined entry and exit criteria;
chair gate reviews and drive go/no-go decisions with engineering and business leaders.
Hold teams and partners accountable to commitments;
detect deviations earlyand drive recovery plans to closure.
Manage multiple concurrent programs and derivatives, balancing priorities and shared resources.
Technical integration
Synchronize MEMS resonator development, ASIC design and verification, package integration and system-level performance so all elements converge on schedule.
Lead tape-out readiness reviews, mask and wafer-start planning, and first-silicon bring-up and characterization plans.
Facilitate trade-off decisions across performance, power, frequency stability, reliability, manufacturability, cost and schedule, and document the outcome.
Ensure every milestone has defined deliverables and measurable exit criteria.
Program budget and cost
Track program spend (NRE, masks, wafers, assembly, qualification lots, test hardware) against plan and forecast variances.
Partner with operations to track product cost against COGS targets through ramp.
Risk, issue and change management
Maintain risk and issue registers with owners, mitigation plans and escalation paths covering technical, schedule, quality and supply-chain risk.
Control changes to requirements, scope and specifications;
assess downstream impact on schedule, cost and customer commitments.
Escalate decisions with clear options, a recommendation and the business impact.
Validation, qualification and manufacturing readiness
Drive characterization, design validation, reliability qualification (JEDEC;
AEC-Q100 where applicable) and production-readiness activities.
Ensure requirements trace to verification and qualification results.
Align fabrication, assembly, packaging and test partners on deliverables, schedules and readiness criteria.
Track test capability, yield, quality, supply and capacity readiness;
drive open issues to closure through ramp.
Customer and stakeholder alignment
Tie program plans to product roadmaps, customer requirements, sample commitments and design-win targets.
Partner with sales and applications on customer milestones, deliverables and customer qualification.
Report program health to engineering leadership and executives in concise, fact-based reviews;
document decisions and follow them through.
Program processes
Build lightweight, scalable program management processes, templates and dashboards suited to a growing fabless company.
Track KPIs: milestone and gate adherence, critical-path health, risk exposure, issue closure and budget variance.
Run retrospectives and feed lessons learned into the next program.
REQUIRED SKILLS
Bachelor's degree in Electrical Engineering, Computer Engineering, Physics or a related technical field;
advanced degree a plus.
8+ years in semiconductor product development, with at least 5 years in engineering program management or technical program leadership.
Owned at least one semiconductor product end to end, from concept through qualification and production release.
Hands-on experience with tape-out, silicon bring-up, characterization, packaging, test and reliability qualification.
Built and run integrated schedules and phase-gate processes;
skilled at critical-path analysis, risk management and recovery planning.
Track record of driving cross-functional teams and external partners to commitments without direct authority.
Clear written and verbal communication, including framing technical trade-offs for executives and customers.
Comfortable making decisions with incomplete information in a fast-moving, resource-constrained startup.
PREFERRED SKILLS
Experience with MEMS devices, oscillators or timing products, or analog/mixed-signal ICs.
Worked directly with foundries, MEMS fabs, OSATs and test houses, ideally in Asia.
Familiarity with JEDEC and AEC-Q100 qualification, PCN/engineering change control and PPAP.
Supported customer sampling, design-in and customer qualification.
Managed program budgets including NRE, masks and qualification spend.
Fabless or early-stage semiconductor company experience.
PMP or equivalent training;
proficiency with MS Project, Smartsheet, Jira, Confluence or similar.
What success looks likeIn the first 90 days:
Integrated Plan of Record published for every active program, with gates, owners and critical path.
Risk register, weekly program review and executive dashboard running.
Within 12 months:
Programs hit committed gate dates, with variances flagged early and recovered.
Customer sample and qualification commitments met, supporting first design wins.
Program spend within forecast;
partners delivering to agreed plans.
Leadership has accurate, real-time visibility into program health and decisions needed.
BENEFITSAt Stathera, we value the well-being and success of our exceptional employees. We offer a comprehensive benefits package that includes:
Health coverage:
Sun Life group insurance plan covering you and your family, 100% paid by Stathera
Wellness:
$500 annual health and wellness allowance
Ownership:
Employee Stock Ownership Plan (ESOP)
Office perks:
Complimentary coffee and snacks
Time off:
Vacation days, personal days and a full December holiday closure
EQUAL OPPORTUNITYStathera is an equal opportunity employer. We are committed to a work environment based on mutual respect, hard work and inclusion, without bias or discrimination. Our team includes people from all backgrounds and walks of life, and each member is valued for what they know and what they can contribute. Together we keep learning, push our boundaries and treat mistakes as chances to grow. Those who do will have the opportunity to grow with us and share in our success. Accommodations are available on request for candidates taking part in all aspects of the selection process.
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INTRODUCTION TO THE ROLEYou will be the single accountable owner for delivering Stathera's semiconductor products, from concept through production release and customer ramp. You own the integrated plan, the schedule, the program budget and the readiness gates, and you are accountable for hitting customer sampling, qualification and design-win commitments.
You will lead a cross-functional team spanning MEMS, ASIC, packaging, test, product engineering, operations and external manufacturing partners. You do not manage these engineers directly;
you drive outcomes through clear plans, sharp decisions and disciplined follow-through. Success means the program ships on time, to spec, at target cost.
Reports to: Chief Operating Officer
Travel: up to 20%, including Asia
What you will ownEnd-to-end program delivery
Own each program from concept and requirements through design, tape-out, first silicon, engineering and customer samples, qualification and production release.
Build and own the integrated Plan of Record: scope, milestones, critical path, dependencies, resources and budget across MEMS, ASIC, package and test.
Run a phase-gate process with defined entry and exit criteria;
chair gate reviews and drive go/no-go decisions with engineering and business leaders.
Hold teams and partners accountable to commitments;
detect deviations earlyand drive recovery plans to closure.
Manage multiple concurrent programs and derivatives, balancing priorities and shared resources.
Technical integration
Synchronize MEMS resonator development, ASIC design and verification, package integration and system-level performance so all elements converge on schedule.
Lead tape-out readiness reviews, mask and wafer-start planning, and first-silicon bring-up and characterization plans.
Facilitate trade-off decisions across performance, power, frequency stability, reliability, manufacturability, cost and schedule, and document the outcome.
Ensure every milestone has defined deliverables and measurable exit criteria.
Program budget and cost
Track program spend (NRE, masks, wafers, assembly, qualification lots, test hardware) against plan and forecast variances.
Partner with operations to track product cost against COGS targets through ramp.
Risk, issue and change management
Maintain risk and issue registers with owners, mitigation plans and escalation paths covering technical, schedule, quality and supply-chain risk.
Control changes to requirements, scope and specifications;
assess downstream impact on schedule, cost and customer commitments.
Escalate decisions with clear options, a recommendation and the business impact.
Validation, qualification and manufacturing readiness
Drive characterization, design validation, reliability qualification (JEDEC;
AEC-Q100 where applicable) and production-readiness activities.
Ensure requirements trace to verification and qualification results.
Align fabrication, assembly, packaging and test partners on deliverables, schedules and readiness criteria.
Track test capability, yield, quality, supply and capacity readiness;
drive open issues to closure through ramp.
Customer and stakeholder alignment
Tie program plans to product roadmaps, customer requirements, sample commitments and design-win targets.
Partner with sales and applications on customer milestones, deliverables and customer qualification.
Report program health to engineering leadership and executives in concise, fact-based reviews;
document decisions and follow them through.
Program processes
Build lightweight, scalable program management processes, templates and dashboards suited to a growing fabless company.
Track KPIs: milestone and gate adherence, critical-path health, risk exposure, issue closure and budget variance.
Run retrospectives and feed lessons learned into the next program.
REQUIRED SKILLS
Bachelor's degree in Electrical Engineering, Computer Engineering, Physics or a related technical field;
advanced degree a plus.
8+ years in semiconductor product development, with at least 5 years in engineering program management or technical program leadership.
Owned at least one semiconductor product end to end, from concept through qualification and production release.
Hands-on experience with tape-out, silicon bring-up, characterization, packaging, test and reliability qualification.
Built and run integrated schedules and phase-gate processes;
skilled at critical-path analysis, risk management and recovery planning.
Track record of driving cross-functional teams and external partners to commitments without direct authority.
Clear written and verbal communication, including framing technical trade-offs for executives and customers.
Comfortable making decisions with incomplete information in a fast-moving, resource-constrained startup.
PREFERRED SKILLS
Experience with MEMS devices, oscillators or timing products, or analog/mixed-signal ICs.
Worked directly with foundries, MEMS fabs, OSATs and test houses, ideally in Asia.
Familiarity with JEDEC and AEC-Q100 qualification, PCN/engineering change control and PPAP.
Supported customer sampling, design-in and customer qualification.
Managed program budgets including NRE, masks and qualification spend.
Fabless or early-stage semiconductor company experience.
PMP or equivalent training;
proficiency with MS Project, Smartsheet, Jira, Confluence or similar.
What success looks likeIn the first 90 days:
Integrated Plan of Record published for every active program, with gates, owners and critical path.
Risk register, weekly program review and executive dashboard running.
Within 12 months:
Programs hit committed gate dates, with variances flagged early and recovered.
Customer sample and qualification commitments met, supporting first design wins.
Program spend within forecast;
partners delivering to agreed plans.
Leadership has accurate, real-time visibility into program health and decisions needed.
BENEFITSAt Stathera, we value the well-being and success of our exceptional employees. We offer a comprehensive benefits package that includes:
Health coverage:
Sun Life group insurance plan covering you and your family, 100% paid by Stathera
Wellness:
$500 annual health and wellness allowance
Ownership:
Employee Stock Ownership Plan (ESOP)
Office perks:
Complimentary coffee and snacks
Time off:
Vacation days, personal days and a full December holiday closure
EQUAL OPPORTUNITYStathera is an equal opportunity employer. We are committed to a work environment based on mutual respect, hard work and inclusion, without bias or discrimination. Our team includes people from all backgrounds and walks of life, and each member is valued for what they know and what they can contribute. Together we keep learning, push our boundaries and treat mistakes as chances to grow. Those who do will have the opportunity to grow with us and share in our success. Accommodations are available on request for candidates taking part in all aspects of the selection process.
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