Fpga Design Engineer
$140k - $160k per yearAversan
FPGA Design EngineerAversan Inc.( ) is a trusted multi-service engineering and electronics manufacturing company. Aversan delivers leading-edge and reliable safety-critical electronics and software systems to the aerospace, defence, and space industries.We are currently seeking a qualified
FPGA Design Engineer
to join our team. The ideal candidate would be able to support the development of next-generation satellite systems and digital payloads.Job Type:
Full-timeWorking Arrangement:
Remote
Responsibilities
Develop custom IP for new features within satellite digital payloads.Improve existing DSP and interface designs to increase reliability.Integrate third-party IP cores and new functionality into FPGA designs.Support the development of communications and network architecture for satellite constellation.Participate in conceptual design studies for future spacecraft.Contribute across the FPGA design lifecycle, including simulation, synthesis, implementation, timing closure, and testing.Collaborate with engineering teams to solve technical problems and deliver working solutions.QUALIFICATIONS:
Bachelor's degree in Computer Engineering, Electrical Engineering, or an equivalent discipline.FPGA/RTL Design: Hands-on FPGA and RTL design experience.HDL Programming: Strong experience with Verilog, SystemVerilog, or VHDL, with a willingness to work with or transition to SystemVerilog.Xilinx Platforms: Experience with Xilinx FPGAs, particularly Zynq and UltraScale.SystemVerilog and Verification: Experience developing RTL, test benches, and testing or verifying FPGA designs.Scripting: Strong Python scripting skills and experience with tools such as Tcl, csh, or Bash.Linux: Experience working in a Linux-based development environment.FPGA Design Flow: Understanding of simulation, synthesis, place and route, timing closure, and hardware testing.Timing: Understanding of timing principles, including clock domain crossing and timing closure.FPGA Tools: Experience with tools such as Xilinx Vivado or Intel Quartus, and HDL simulation tools such as ModelSim.Compensation: $140,000 - $160,000 CAD (annual salary)The base salary or rate offered to an applicant within this range is determined by considering several factors, including the individual's geographic location, skills, competencies, and unique qualifications. This ensures compensation is fair and aligned with the specific requirements and attributes of each candidate.Vacancy Status: This posting is for an existing vacancy.AI in Hiring: We use AI tools to assist with application management (e.G., organizing submissions and surfacing potentially relevant qualifications). AI is not used to make hiring decisions. All decisions are made by our hiring managers and recruitment team. Our use of AI is governed by security and privacy risk assessments aligned with our cybersecurity framework.#J-18808-Ljbffr
FPGA Design Engineer
to join our team. The ideal candidate would be able to support the development of next-generation satellite systems and digital payloads.Job Type:
Full-timeWorking Arrangement:
Remote
Responsibilities
Develop custom IP for new features within satellite digital payloads.Improve existing DSP and interface designs to increase reliability.Integrate third-party IP cores and new functionality into FPGA designs.Support the development of communications and network architecture for satellite constellation.Participate in conceptual design studies for future spacecraft.Contribute across the FPGA design lifecycle, including simulation, synthesis, implementation, timing closure, and testing.Collaborate with engineering teams to solve technical problems and deliver working solutions.QUALIFICATIONS:
Bachelor's degree in Computer Engineering, Electrical Engineering, or an equivalent discipline.FPGA/RTL Design: Hands-on FPGA and RTL design experience.HDL Programming: Strong experience with Verilog, SystemVerilog, or VHDL, with a willingness to work with or transition to SystemVerilog.Xilinx Platforms: Experience with Xilinx FPGAs, particularly Zynq and UltraScale.SystemVerilog and Verification: Experience developing RTL, test benches, and testing or verifying FPGA designs.Scripting: Strong Python scripting skills and experience with tools such as Tcl, csh, or Bash.Linux: Experience working in a Linux-based development environment.FPGA Design Flow: Understanding of simulation, synthesis, place and route, timing closure, and hardware testing.Timing: Understanding of timing principles, including clock domain crossing and timing closure.FPGA Tools: Experience with tools such as Xilinx Vivado or Intel Quartus, and HDL simulation tools such as ModelSim.Compensation: $140,000 - $160,000 CAD (annual salary)The base salary or rate offered to an applicant within this range is determined by considering several factors, including the individual's geographic location, skills, competencies, and unique qualifications. This ensures compensation is fair and aligned with the specific requirements and attributes of each candidate.Vacancy Status: This posting is for an existing vacancy.AI in Hiring: We use AI tools to assist with application management (e.G., organizing submissions and surfacing potentially relevant qualifications). AI is not used to make hiring decisions. All decisions are made by our hiring managers and recruitment team. Our use of AI is governed by security and privacy risk assessments aligned with our cybersecurity framework.#J-18808-Ljbffr
Vacancy posted 2 hours ago
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