ASIC Automation Intern for Next-Gen DSP & Verification

Ciena Corporation in Ottawa is seeking an ASIC Engineer Intern to support automation infrastructure for next‑generation ASIC devices. You will work with the design, layout, integration, and verification teams on DSP ASIC development for optical communications.

The role offers exposure to SystemVerilog/UVM verification, Python-based tooling, and Linux environments, with mentorship and a 4–8 month term starting January 2027. Paid internship with competitive benefits and holidays.