Lead Rtl Verification Engineer

Lead RTL verification with Cadence in Montreal, applying SystemVerilog and reusable environments to high-performance physical IP development. This full-time role requires office work.As Lead Verification Engineer, you will verify digital RTL and develop reusable verification components and environments. You will contribute to flow development, test planning, execution, functional coverage closure, and code coverage closure. Collaboration spans design, verification, project management, and digital and analog teams.Key Responsibilities:
Verify digital RTL for industry-standard protocol physical IPDevelop reusable verification components and environmentsDevelop verification flows and test plansExecute tests and close functional coverageCommunicate project progress across technical teamsRequirements:
Bachelor's degree in electrical, computer engineering, or computer scienceUnderstanding of verification architecture, methodologies, and Metric Driven VerificationKnowledge of UVM and SystemVerilog AssertionsUnderstanding of digital design flow and coverage planningAbility to communicate in EnglishApply digital verification, SystemVerilog, coverage, and collaboration skills to Cadence physical IP projects in Montreal.
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