Senior High-Speed Analog Layout Lead
Celero Communications, Inc.
Celero Communication Inc. is seeking a Principal/Senior Analog Layout Engineer to drive the layout of analog/mixed-signal IP blocks for high‑performance optical communication systems.
You will collaborate with circuit designers, CAD/PDK teams, and other layout engineers to ensure first‑pass silicon success. You will lead floor planning, layout of ADCs/DACs/PLLs, mentor junior engineers across time zones, and perform LVS, DRC, PERC signoffs.
#J-18808-Ljbffr$105k - $122k per year
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