Senior Asic Physical Design Leader

Lead ASIC physical design for Cisco Silicon One hardware, specializing in fullchip floorplanning, RTL-to-GDSII implementation, and timing closure.As an ASIC Development Technical Leader, you will shape physical design methodology within Cisco’s Common Hardware Group. Your work spans hierarchical implementation, power integrity, physical verification, and performance, power, and die-size optimization. You will collaborate with system, package, RTL, DFT, implementation, EDA vendor, and tool-flow teams.Key Responsibilities:
Develop fullchip floorplans using architecture and foundry guidelinesPerform partitioning, pin assignment, clock, and bump planningExecute RTL-to-GDSII implementation and physical verificationAnalyze flows and implement methodology enhancementsDefine signoff methods with foundry and standard-cell vendorsRequirements:
Bachelor’s degree and eight-plus years’ physical design experienceMaster’s degree and six-plus years’ physical design experiencePhD and three-plus years’ physical design experienceRTL2GDSII and tapeout experience at 7nm, 5nm, or 3nmExperience with Innovus, Tempus, PrimeTime, RedHawk, Voltus, Calibre, or PegasusApply fullchip physical design, timing, power integrity, and implementation expertise to Cisco’s advanced ASIC platforms.
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