Pci Express Rtl Design Engineer

Apply Verilog HDL and RTL quality expertise to AMD PCI Express subsystem integration, synthesis, timing, lint, and CDC closure.This ASIC Design Engineer role centers on PCIe IP Enablement across architecture, IP design, implementation, and SoC integration. You will help deliver accurate, high-quality designs while working with IP designers, Physical Design teams, and SoC-level leads. The position includes technical problem-solving, debugging, and flow automation.Key Responsibilities:
Design and develop PCIe IP and related digital subsystemsDrive synthesis, lint, CDC, equivalence, and timing closureSupport subsystem integration, implementation, and SoC deploymentImplement clock, test, and debug-related design requirementsIdentify technical issues and guide solution directionRequirements:
Proven ASIC design experience through architecture to tape-outStrong understanding of RTL and Verilog HDLExperience with RTL quality and design flow toolsUnderstanding of power-saving techniques and power-aware checksExcellent problem-solving, communication, and debugging skillsUse PCIe, RTL, synthesis, CDC, and subsystem integration skills to advance AMD digital design programs.
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