Logic Equivalence Checking Engineer

Develop formal equivalence methodologies for complex SoC designs using Cadence Conformal, Synopsys Formality, and automation scripting.As a LEC CAD Engineer, you will support functional correctness across RTL, synthesized netlists, and physical designs. You will own sign-off methodologies, enable ECO flows, debug non-equivalences, and optimize verification tools. Your work spans RTL-to-GDS and gate-to-gate flows.Key Responsibilities:
Own end-to-end LEC sign-off methodologies across design flowsEnable ECO flows for safe late-stage design modificationsDebug non-equivalences, aborts, and mismatches across stagesMaintain Tcl, Python, Perl, or Shell automationOptimize verification tool runtime, capacity, and scalabilityRequirements:
Proficiency with Cadence Conformal LEC and ECO toolsProficiency with Synopsys FormalityBachelor's or Master's degree in Electrical EngineeringDegree in Computer Science or related fieldDedicated hardware or EDA experienceApply formal verification, ECO, debugging, and automation expertise to support functional correctness throughout complex SoC development.
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