System & Fpga Platform Engineer

About SymaticsSymatics is a Singapore-headquartered fabless semiconductor startup building the MPU, a deterministic AI inference accelerator for large language models. Instead of scheduling work at runtime, the MPU executes a compiler-generated static schedule across a large on-die compute array and a low-latency multi-chip fabric, on a 5nm-class node with commodity GDDR memory. The target is predictable, low-latency inference for MoE and agentic workloads at rack scale.
The founding team comes from ATI/AMD, Lightelligence, eTopus and the wider GPU, SerDes and AI-silicon community. Toronto is our MPU design centre;
Hsinchu is the centre for the fabric switch.
What you will doOwn the path from architecture to a working system: FPGA proof-of-concept today, board/host/rack-level definition for silicon next.
Build and maintain the multi-FPGA prototype (AMD Versal / Alveo class, HBM and PAM4 transceivers) — Toronto will host one of two lab rigsPort and partition RTL to FPGA;
timing closure, transceiver bring-up, host PCIe link, debug infrastructureDefine system-level requirements: host interface, board, power, thermal, clocking/synchronisation across many acceleratorsWrite bring-up plans and lab validation procedures for first siliconWork with software on drivers, firmware and demo workloads
What we are looking forBS/MS EE/CE;
7+ years in FPGA prototyping, system/board design or silicon bring-upStrong Vivado / Versal flow;
multi-gigabit transceivers;
PCIe endpoint designLabskills: scopes, BERT, protocol analysers;
methodical debugScripting (Python/Tcl) and basic Linux driver-level literacy
Nice to haveRack-scale or multi-accelerator system design (GPU servers, switch systems)SI/PI awareness for 32G NRZ / 64G PAM4 linksPost-silicon validation of GPU, NPU or networking ASICs
Pay: $145,000.00-$185,000.00 per year
Work Location: In person
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