Principal Packaging Engineer

Semtech's Signal Integrity Products (SIP) Business Unit delivers high-performance mixed-signal ICs for the data communications and video broadcast industries — powering the interconnects that move data inside the world's largest hyperscaler data centers. Our Packaging Technology team sits at the heart of this mission, bridging the gap between silicon and system through world-class IC package design, signal integrity engineering, and close collaboration with a global network of advanced manufacturing partners.

You will be joining a highly integrated team of digital, analog, physical, and systems engineers who are passionate about solving hard problems at the intersection of speed, density, and reliability. If you thrive in a technically challenging, fast-moving environment where your work directly impacts next-generation Datacenter connectivity products — this is your team.

As a Principal Engineer in IC Package Design and Signal Integrity, you will lead the design and electrical characterization of advanced high-speed IC packages for Semtech's Datacenter connectivity product portfolio. Your primary responsibilities will span 3D electrical signal integrity modeling, IC package layout, and cross-functional collaboration across design, manufacturing, quality, and reliability engineering disciplines.

This role requires a deep understanding of high-speed transmission line behavior, advanced packaging architectures, and the full NPI lifecycle from concept through qualification. You will work closely with internal teams and external manufacturing partners, serving as a key technical authority on package-level signal and power integrity. The ideal candidate brings strong hands‑on experience in EDA tooling, RF/SI measurement, and a track record of delivering complex package designs into high-volume production.

• Design high-speed IC packages and Chip‑On‑Board (COB) solutions to meet new product technical and financial requirements;
  develop robust solutions that achieve the highest levels of quality and reliability in fast‑paced Datacenter connectivity environments.
• Perform 3D signal integrity modeling at silicon, package, and system levels, including experimental validation via Scattering Parameter (S‑parameter) and Time‑Domain Reflectometer (TDR) measurements where required.
• Prepare technical reports and application notes for internal teams and external customers/suppliers, covering Signal and Power Integrity (SI/PI), PCB layout guidance, and assembly process instructions.
• Design and produce PCB and high‑density substrate layouts for reliability qualification and electrical performance evaluation.
• Serve as technical interface with manufacturing suppliers throughout new product introduction (NPI), package definition, and design phases;
  drive alignment betweendesign intent and manufacturing capability.
• Identify, evaluate, and launch projects with new strategic suppliers and emerging package technologies to advance Semtech's packaging roadmap.
• Mentor junior packaging engineers and contribute to continuous improvement of design methodologies, tools, and workflows.

• Bachelor's degree in Electrical Engineering, Physics Engineering, or a related field, with 8+ years of experience as an IC Package Design Engineer or Signal Integrity Engineer.
• Deep expertise in high-speed transmission line theory, multi‑domain power delivery network (PDN) design, and package-level signal integrity — including crosstalk, impedance control, and return‑loss optimization.
• Hands‑on proficiency with industry‑standard EDA tools: Keysight Advanced Design System (ADS), Cadence Advanced Package Designer (APD/SiP), and Ansys HFSS.
• Demonstrated experience with RF/SI measurement equipment including Vector Network Analyzers (VNA) and Time‑Domain Reflectometers (TDR).
• Familiarity with multiple advanced packaging technologies: 2D, 2.5D, 3D, Fan‑In, Fan‑Out (FOCOS), high‑density substrate, silicon bridge interconnects, and Chip‑On‑Board (COB).
• Experience in optoelectronics package design or opto‑electronic assembly is a strong asset.
• Working knowledge of JEDEC specification JESD47H (Stress‑Test‑Driven Qualification of Integrated Circuits) and its design implications.
• Proven ability to manage supplier relationships and drive technical alignment throughout NPI and package qualification phases.
• Strong written and verbal communication skills, with the ability to produce high‑quality technical documentation for both internal and customer‑facing audiences.

• Master's degree or Ph.D. in Electrical Engineering, Physics, or a related discipline.
• Experience with opto‑electronic package assembly and photonic integration is highly desirable.
• Background in Datacenter or high‑speed communications product development (400G, 800G, 1.6T).
• Familiarity with thermo‑mechanical simulation tools and reliability engineering methodologies (e.G., finite element analysis for package stress modeling).
• Experience working in a fabless semiconductor environment with global contract manufacturing partners.

We are proud to be an EEO employer M/F/D/V. We maintain a drug‑free workplace.

A reasonable estimate of the pay range for this position is $150,000 - $164,000. There are several factors taken into consideration in determining base salary, including but not limited to: job‑related qualifications, skills, education and experience, as well as job location and the value of other elements of an employee’s total compensation package.