Physical Design Engineering Director Toronto

Lead physical design for high-speed connectivity ASICs as Astera Labs’ Physical Design Engineering Director, fully on-site in Toronto.You will guide implementation from RTL to GDSII for PCIe retimers, Ethernet retimers, and signal conditioning solutions. The role combines hands-on technical leadership with people management across floorplanning, place-and-route, timing closure, and sign-off. You will build the Toronto physical design team for the Signal Connectivity Group.Key Responsibilities:
Lead physical design execution from floorplan through tapeoutDrive synthesis, place-and-route, CTS, extraction, and timing closureCoordinate design convergence with RTL, DFT, STA, EMIR, and verificationMentor engineers, hire team members, and plan sprintsCoordinate methodology with global physical design teamsRequirements:
Bachelor’s degree in electrical or computer engineering15+ years implementing complex SoCs at 7nm or below5+ years leading teams or projectsExperience with Cadence Innovus or Synopsys Fusion Compiler or ICC2Scripting ability in Tcl, Python, or PerlBring physical design leadership, advanced-node implementation, and team-building expertise to Astera Labs’ Toronto connectivity programs.
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