ASIC Digital Backend Physical Design and DFT Engineer

Job Responsibility: Ciena is committed to our people-first philosophy. Our teams enjoy a culture focused on prioritizing a personalized and flexible work environment that empowers an individual's passions, growth, wellbeing and belonging. We're a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact. How You Will Contribute: The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions, and are one of the main contributors to Ciena's success in the telecommunications industry. As a Digital ASIC Physical Design Engineer working on large mixed-signal SoC ASICs targeting advanced technology nodes, you'll play a key role in floorplan development for physical aware synthesis and PnR, block level Place and Route implementation including routing congestion analysis, CTS, power and IR-drop optimizations and timing closure. In addition to Place & Route, you will be responsible to run STA, generate and implement timing ECOs as well as power integrity and physical verification. Your ability to innovate and drive solutions optimized for performance, power and area for the Wavelogic ASICs will be key.

• You will scope the design physical architecture, and work with EDA vendor tools to build, adapt, and maintain a successful flow from netlist to full closure and GDSII generation.
• Partnering with RTL circuit designers and other layout engineers, you will create adequate floorplan, design power grid and clock distribution networks to accomplish optimal performance.
• Understand and navigate the various EDA tool settings, parameters, and attributes to be able to drive the tool for signoff quality and closure with optimal PPA.
• You will identify and suggest alternative implementations, recommendations, and solutions pointing out lower power and higher performance trade-offs.
• You will work with analog designers and ASIC/SoC in integrating analog blocks.
• You will be responsible for running initial trials of quick PnR to refine the design and correlation. In working with the RTL designers and architects to understand the circuit data flow, you will influence circuit architecture to achieve reliable and closable physical design.
• You will generate and implement timing ECOs to help closure and implement functional ECOs to apply an RTL feature fix when needed. You would be exposed to running formal verification (LEC or Formality) and analyzing the reports.
• You will write scripts to improve productivity and efficiency of your work as well as the work of other backend engineers. In the process, you will interact with tool and technology vendors to drive tool fixes, flow improvements, and perform evaluations of new tools and tool features.
• You will produce a concise status report at various stages of the development and highlight trade-offs.
• You are expected to understand DFT requirements of the block from ASIC service provider. Using the necessary physical aware feature of the synthesis tool to reduce timing issue associated with layout and/or ECO.
• Using the necessary scan chain reordering and placement/CTS constraints, you will work to resolve timing issues associated with DFT.
• You will be exposed to running STA, analyzing timing reports and debugging issues related to timing constraints, missing exceptions, correlation between P&R and STA tools, etc.

The above lists are intended to describe the general nature and level of work, and they are not intended to be a comprehensive list of all responsibilities, duties and skills required to be qualified and to be performed by the selected candidate. You will have an opportunity to better understand the role through the interview experience. The Must Haves:

• Minimum Bachelor's degree in Electrical or Computer Engineering, Computer Science or other applicable scientific degree coupled with significant experience in ASIC physical digital design and timing closure
• Understanding of the submicron technology nodes full backend ASIC flow and timing/power/area analysis and trade-offs.
• Proven experience working with Genus, Innovus, and PrimeTime.
• Practical experience developing scripts to automate tasks throughout the backend flow.
• Experience in working with multiple power domains and knowledge of UPF and SOCV/POCV concepts

Assets:

• Experience with Tempus, Redhawk/Voltus, and Calibre.

Pay Range: The annual pay range for this position is $100,900 - $161,100. Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available. Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence. Not ready to apply? Join our Talent Community to get relevant job alerts straight to your inbox. At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination. Ciena is an Equal Opportunity Employer, including disability and protected veteran status. If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.