Soc Formal Verification Cad Engineer

Support complex SoC development through formal verification, RTL-to-GDS sign-off, and debugging across multiple design stages.This LEC CAD Engineer develops and supports methodologies that verify functional correctness between RTL, synthesized netlists, and physical designs. The position manages flow requirements, enables Engineering Change Order implementation, and investigates non-equivalences. It also includes automation with Tcl, Python, Perl, or Shell and collaboration with EDA vendors.Key Responsibilities:
Maintain RTL-to-GDS and gate-to-gate sign-off flowsImplement ECO methodologies for late-stage design changesAnalyze non-equivalences, aborts, and design mismatchesDevelop scripts and automation infrastructure for verificationPartner with EDA vendors on tool optimizationRequirements:
Knowledge of Cadence Conformal LEC and ECOKnowledge of Synopsys FormalityBachelor's or Master's degree in Electrical EngineeringComputer Science or related academic backgroundDedicated hardware or EDA experienceBring LEC methodology, ECO implementation, automation, and root-cause analysis skills to complex SoC verification flows.
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