Senior FPGA RTL Designer

Design complex FPGA systems at Fidus using RTL, Verilog, and VHDL while collaborating with customers and cross-functional teams across Canada. Travel may be required.

As an FPGA Designer, you will define architectures, implement RTL, integrate IP, simulate designs, and close timing. The work spans video, communications, storage, and signal processing applications. You will use Xilinx and Intel devices and tools while supporting high-complexity electronic products.

Key Responsibilities:

• Develop FPGA and CPLD systems with Fidus clients and teams
• Design with Xilinx and Intel devices and development tools
• Integrate IP, run simulations, and complete timing closure
• Test and debug prototypes in the laboratory
• Author test plans, design descriptions, and user documentation

Requirements:

• Minimum five years designing FPGA RTL with Verilog or VHDL
• Experience with SystemVerilog, Vivado, Quartus, or ModelSim
• Knowledge of verification, test benches, simulations, and timing closure
• Degree in B.A.Sc., B.Eng., or equivalent
• Fluent English and strong customer communication skills

Apply FPGA architecture, RTL design, verification, and timing expertise to complex Fidus client systems across emerging technology markets.