Advanced Node Sta Architect

Advance 3nm-and-below STA and design closure at Cadence through deep timing expertise, flow customization, and technical influence.This architect focuses on advanced-node signoff and closure solutions spanning digital design, ECOs, constraints, UPF, hierarchical STA, and 3DIC design. You will lead complex benchmarks, customize flows with scripting, and guide customer adoption across 5nm-and-below technologies. Collaboration with R&D and Product Engineering informs tool enhancements.Key Responsibilities:
Lead advanced-node benchmarks and timing closure flow optimizationsGuide customer adoption of signoff and AgenticAI capabilitiesDeploy methodologies for STA, IR Drop, and power closureCollaborate with R&D and Product Engineering teamsPosition Cadence through technical industry presentationsRequirements:
15+ years in IC design implementation and signoffDeep expertise in 3nm-and-below STA and ECOsExperience debugging UPF and constraints across complex designsStrong Tcl, Python, Perl, and flow customization proficiencyProven executive-level customer success and technical team leadershipUse advanced-node STA, closure methodologies, and scripting expertise to solve complex Cadence customer design challenges.
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