Mixed Signal Custom Layout - Temporary/Seasonal
AMD
Job Description ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. THE ROLE: The full custom IC layout group is looking for a candidate to design the layout for digital and analog circuits based on schematics using industry leading CAD tools and cutting edge foundry technology. Examples of layout designed by our team include Phase Locked Loop (PLL), Delay Locked Loop (DLL), Voltage Controlled Oscillator (VCO), Digital to Analog Converter (DAC), Current Regulator, High Speed Differential Signaling circuitry, Droop Detect, and Die Crack Monitor. Proficiency in 2D layout design while being able to visualize in 3D space are traits ideal for this position. It is useful to have knowledge of digital and analog circuitry at the CMOS transistor level. THE PERSON: The candidate will be able to see through the different stages of a project development – from initial floor planning and routing of low level logic gates through top level integration of numerous blocks and ultimately, project tape out related tasks. Day to day responsibilities include layout of lower level cells and assembly of these lower level cells into IPs. You will be running various verification tools at all levels of the design hierarchy. These include DRC, LVS, EM/IR, ERC and Latch up/ESD.Over time, responsibilities will expand to include guiding and coordinating off‑shore contractors performing layout tasks. KEY RESPONSIBILTIES:
- Create clean, robust layouts for digital and analog building blocks at the transistor level in Cadence Virtuoso.
- Floorplan, route, and assemble lower-level cells into macros
- Build black-box/abstract models and views consumed by other teams; contribute to tapeout collateral for custom blocks.
- Run hierarchical checks at cell/macro levels (DRC, LVS, ERC, EM/IR, Latch-up/ESD) and iterate to closure in partnership with circuit owners.
- Explore and leverage AI-assisted tools and workflows to improve layout productivity, verification efficiency, and design quality.
- Strong understanding of CMOS device/circuit theory and analog/digital layout best practices.
- Proficiency with industry-standard layout tools (e.g., Virtuoso, Calibre)
- Experience with LVS, DRC, EMIR and other physical verification flows
- Exposure to advanced nodes (e.g., 2nm/3nm; experience at 5nm/7nm also valued).
- Background with IP/standard-cell layout, high-speed differential signaling, PLL/DLL/VCO, DACs, power pads, and in-context XOR.
- Scripting/automation in Perl, TCL, SVRF/TVF, SKILL is a plus
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