Design Verification Lead - PCIe/CXL IP Expert
AMD
AMD in Markham, ON is seeking a Design Verification Engineer Lead to drive front-end verification for FPGA and ASIC IP, delivering first-pass silicon for PCIe and CXL solutions. You will collaborate with architecture, IP, physical design, firmware and product engineering teams to ensure robust verification across the full development lifecycle.
Lead the verification effort, build UVM environments, develop directed and constrained randomness tests, run regressions, debug failures, and push
#J-18808-LjbffrVacancy posted 3 days ago
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