Senior Serdes Verification Engineer

Validate Backplane Ethernet, PCIe, SATA, and USB SERDES at Synopsys from Markham or Mississauga.As a senior ASIC verification engineer, you will help deliver mixed-signal designs through test planning, functional testing, and performance validation. The position combines Verilog, SystemVerilog, UVM, VMM, assertions, and coverage-driven verification. Collaboration with digital and analog engineers is central to the work.Key Responsibilities:
Verify current and next-generation SERDES productsPlan functional and performance testing for test chips and productsBuild constrained-random and coverage-driven verification environmentsAnalyze functional, code, and assertion coverageDebug complex testbench and design-related issuesRequirements:
BS or MS in Electronics, Electrical Engineering, or related discipline8+ years of digital verification methodology experienceSolid Verilog and SystemVerilog test case development experienceSolid understanding of digital circuit designSystemVerilog Assertions or formal verification knowledge is desiredUse SERDES verification, mixed-signal collaboration, and coverage expertise to support Synopsys connectivity products.
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