Fpga Rtl Design Engineer

Design complex FPGA systems at Fidus using RTL, Verilog, and VHDL while collaborating with customers and cross-functional engineering teams in Canada.As an FPGA Designer, you will define architectures, implement RTL, integrate IP, run simulations, close timing, and support lab bring-up. Your work spans video, communications, storage, and signal processing applications. You will use Xilinx and Intel devices and tools while producing documented, high-quality designs.Key Responsibilities:
Develop FPGA and CPLD architectures with customers and Fidus teamsImplement RTL, integrate IP, simulate designs, and close timingConduct design reviews against requirements and quality standardsTest and debug prototypes in the laboratoryAuthor test plans, design descriptions, and user documentationRequirements:
Minimum five years designing FPGAs with RTL, Verilog, or VHDLExperience with Xilinx or Altera families and tool flowsKnowledge of SystemVerilog, Vivado, Quartus, or ModelSimExperience with verification, test benches, simulations, and timing closureB.A.Sc., B.Eng., or equivalent degree and fluent EnglishApply FPGA architecture, RTL implementation, verification, and timing closure skills to complex client systems at Fidus.
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