Low Latency Java Developer, Vice President

Role SummaryThe Applications Development Technical Lead Analyst is a senior engineering and architectural leadership role, within the global Client Risk and Position Management technology organization.
In this capacity, you will serve as the principal designer, systems architect, and hands‑on lead engineer for mission-critical, low latency, and high-throughput risk platforms. These platforms power real‑time credit checks, intraday position aggregation, margin valuation, anomaly detection, and live risk limit enforcement across global trading desks.
As an engineering leader, you will collaborate extensively with other global teams and stakeholders across Asea, Europe, and Americas. You will champion modern engineering practices - actively designing, building, and prototyping using AI‑augmented tools such as GitHub Copilot, Devin, and generative coding assistants to accelerate development of lifecycles, elevate code quality, and modernize enterprise architectures. Additionally, you will serve as the primary regional and global technical contact for Risk Managers, Product Owners, Front‑Office Trading Desks, and cross‑functional technology partners.
Key Responsibilities
Architect & Design: Lead the end-to-end technical architecture and low-level design for distributed, fault-tolerant, high-concurrency risk calculation and position management engines supporting global trading sessions.
Hands‑on Development: Actively write, review, and optimize high-performance, multi-threaded production code primarily in Java (Java 17/21+), with targeted high-performance/low-latency modules in C++ and exploring Rust where ultra‑low latency memory safety and deterministic execution are required.
AI-Augmented Engineering: Champion the adoption of modern AI development workflows (e.G., GitHub Copilot, Devin, AI-driven code review, and automated test generation) to enhance developer productivity, modernize legacy components, and accelerate time-to-market.
Middleware & Event Streams: Design resilient, low-latency, event-driven pipelines using enterprise messaging backbones such as Apache Kafka, Solace PubSub+, and other low-latency middleware fabrics.
Performance Tuning: Profile, benchmark, and optimize CPU usage, memory layout, GC overhead, network serialization, and IPC for microsecond/sub-millisecond level latency.
Global Stakeholder Collaboration & Technical Advisory
Key Technical Liaison: Act as a technical contact and subject matter expert (SME) for Risk Managers, Product Owners, Trading Desks, Quantitative Analysts, and Operations across APAC and global hubs.
Global Team Alignment: Partner closely with regional and global engineering pods across Singapore, London, New York, and other tech centers to ensure seamless platform rollouts, operational stability, and cohesive architecture standards.
Cross-Technology Coordination: Interface closely with upstream Order Management Systems (OMS), Execution Management Systems (EMS), Market Data feeds, and downstream Clearing/Settlement and Regulatory reporting platforms across multiple asset classes (FX, Equities, Rates, Commodities, Credit).
Requirement Translation: Translate complex quantitative risk models, margin methodologies, and regional/global regulatory requirements into scalable, deterministic technical architecture
Mentorship & Regional/Global Leadership
Lead, coach, and mentor mid-level and junior engineers in Singapore and regional teams in distributed systems design, clean code practices, and modern AI-assisted engineering techniques.
Lead architectural design reviews and rigorous peer code reviews to ensure reliability, security, and maintainability across distributed codebases.
Partner with engineering managers and Scrum Masters across time zones on sprint planning, technical estimations, dependency resolution, and milestone delivery.
Technical Proficiencies
Java: Proficiency in modern Java (17/21+), JVM internals, memory management/profiling, lock-free data structures, concurrent programming, and low-latency tuning.
C++ / Rust (Desirable): Practical experience or working knowledge of C++ (14/17/20) and/or Rust for performance-critical, memory-safe, or low-latency system components and cross-language interoperability (JNI, FFI)
Education
Bachelor's degree / University degree in Computer Science, Computer Engineering, Software Engineering, or equivalent STEM discipline.
Master's degree (Desirable) in Computer Science, Financial Engineering, or related quantitative field
Job Family GroupTechnology
Job FamilyApplications Development
Time TypeFull time
Primary Location Full Time Salary Range$120,800.00 - $170,800.00
Automated Processing and AIWe use automated processing, including artificial intelligence, for our legitimate business interests (or our reasonable and appropriate business purposes) to identify and align the candidate's skills and abilities with a specific job opening. Additionally, if you so choose, or consent, we can match your skills and abilities to other suitable roles at Citi.
Importantly, all our hiring processes and decisions, including determining your suitability for a role, are conducted, checked, and decided by individuals. Our automated processing and AI do not involve relying on automatic or autonomous decision‑making. Please refer to any Jurisdictional Considerations, with specific provisions for your country (where relevant) for further details.
Equal Opportunity and Accessibility StatementCiti is an equal opportunity employer, and qualified candidates will receive consideration without regard to their race, color, religion, sex, sexual orientation, gender identity, national origin, disability, status as a protected veteran, or any other characteristic protected by law.
If you are a person with a disability and need a reasonable accommodation to use our search tools and/or apply for a career opportunity review Accessibility at Citi.
View Citi’s EEO Policy Statement and the Know Your Rights poster.
#J-18808-Ljbffr