Lead ASIC Verification Engineer Position

Join the forefront of technology as a Senior ASIC Verification Engineer. Shape the future of SoC development through robust verification environments and high-level collaboration across teams. This independent contributor role focuses on developing verification strategies and executing complex test plans for ASIC designs. With a minimum of 8 years in the field, you will collaborate closely with engineers to enhance silicon delivery. Expertise in SystemVerilog, UVM, and verification methodologies is essential for this role. Key Responsibilities:

• Design and verify SoCs with advanced verification techniques
• Create robust testing environments and self-checking generators
• Develop verification tests for ASIC designs at various levels
• Engage with cross-functional teams to resolve complex issues
• Assist in the integration and debugging process

Requirements:

• Bachelor’s degree in Electrical Engineering or a related field
• 8+ years in ASIC verification or related experience
• Proficient in SystemVerilog, UVM, and Python
• Experience with functional coverage principles
• Strong analytical and communication capabilities

Utilize your extensive verification skills to deliver exceptional results in cutting-edge ASIC projects. #J-18808-Ljbffr