Senior Rtl Design Engineer

Design complex digital integrated circuits in Burnaby using SystemVerilog and Verilog. Support ASIC validation, debugging, and implementation decisions.As a Senior Engineer I-Design, you will contribute to Microchip’s Data Center Solutions business unit under experienced leaders. The work covers RTL design for blocks, subsystems, or devices ranging from 100K to 50M+ gates. You will collaborate with design, verification, architecture, and physical design teams on storage and computer interface products.Key Responsibilities:
Design digital integrated circuits using Verilog and SystemVerilogDefine features and document implementation detailsSupport emulation, ASIC validation, debugging, and workaroundsResolve technical issues with distributed design and verification teamsJustify implementation decisions and trade-offs with architectsRequirements:
Bachelor’s or master’s degree in electrical or computer engineeringThree to five years of related experienceExperience with complex ASIC design flows and RTL designKnowledge of synthesis, static timing analysis, and physical designAnalytical, debugging, communication, teamwork, and time management skillsApply digital design, ASIC flow, and debugging expertise to Microchip’s Data Center Solutions products in Burnaby.
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