Senior Fpga Rtl Designer

Design complex FPGA systems at Fidus using RTL, Verilog, and VHDL while collaborating with customers and cross-functional teams across Canada. Travel may be required.As an FPGA Designer, you will define architectures, implement RTL, integrate IP, simulate designs, and close timing. The work spans video, communications, storage, and signal processing applications. You will use Xilinx and Intel devices and tools while supporting high-complexity electronic products.Key Responsibilities:
Develop FPGA and CPLD systems with Fidus clients and teamsDesign with Xilinx and Intel devices and development toolsIntegrate IP, run simulations, and complete timing closureTest and debug prototypes in the laboratoryAuthor test plans, design descriptions, and user documentationRequirements:
Minimum five years designing FPGA RTL with Verilog or VHDLExperience with SystemVerilog, Vivado, Quartus, or ModelSimKnowledge of verification, test benches, simulations, and timing closureDegree in B.A.Sc., B.Eng., or equivalentFluent English and strong customer communication skillsApply FPGA architecture, RTL design, verification, and timing expertise to complex Fidus client systems across emerging technology markets.
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