Senior Asic Design Verification Engineer

Lead ASIC verification for Snap Inc.’s Spectacles Team, using UVM, SystemVerilog, and Siemens Questa in an office-based model.This engineer designs verification for display Integrated Circuits supporting augmented reality. The work spans digital design, analog logic, software, and verification collaboration. You will build testbenches, execute coverage-driven plans, automate tools, and debug simulations.Key Responsibilities:
Design display Integrated Circuits for augmented realityDevelop UVM-based and assertion-based testbenchesCreate functional and code coverage verification test plansUse Siemens Questa for verification and debuggingSpecify tools and create automationRequirements:
BSEE, MSEE, or relevant years of experience10+ years of ASIC Design Verification experienceStrong UVM and SystemVerilog knowledgeDigital simulation and Verilog RTL practicesLinux scripting with TCL, Make, Perl, Python, or ShellApply ASIC verification expertise, coverage planning, SystemVerilog, and automation to Snap’s AR display circuit development.
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